Platform Xeon + FPGA Acceleration Managed and led the design and verification of multiple generations of CXL devices. Led the development of Altera's CXL IP which supports Type 1, 2, 3 and a base/CPI mode. CXL IP handles all CXL protocol details. Includes a coherent cache for host and device memory.Drove roadmap, feature architecture, example designs and performance improvements.Led development of first CXL devices in Intel. Used to validate CXL on multiple generations of Xeon products. Fully coherent validation solutions to validate all cache/mem opcodes. Evolved solutions across multiple CXL specification versions.

Design and verification manager for L3 Cache controller, Point of Serialization and Snoop filter for three generations of Centriq server as well as Snapdragon 820. Design in System Verilog. Verification in UVM. Led the L3 team to support HW managed coherency across multiple die, the addition of a chip to chip snoop filter, sectoring, and quality of service including bandwidth control, capacity controls and capacity monitoring. Closely coupled to CPU over coherent bus.Drove functional and code coverage closure for key milestones across multiple tapeouts. Created detailed project plans and leveraged priorities in MS Project to create schedules that can be updated, reallocated and recalculated easily. DDR Mobile memory controller designer for multiple Snapdragon tapeouts. Implemented in System Verilog with support for LPDDR2, LPDDR3, and DDR3. Primarily responsible for maintenance command scheduler (e.g. self-refresh, auto refresh including per bank refresh, ZQ cal, derated timing, CA training, tREFBW, write leveling). Designed a new unit to allow SW to program parameters in time based units directly from datasheets. Optimized Synthesis flow. Drove 0-in CDC analysis and waivers. Timing take down.Sole designer for audio interfaces in multiple Snapdragon generations. PCM, single-channel I2S, Multi-channel I2S, and digital microphone. Included HW mixer and AHB based DMA controller. Responsible for all block level tool flows and signoff including synthesis, lint (Spyglass PLDRC), Cadence LEC and 0-in Clock Domain Crossing analysis.

Responsible for the VHDL design of the transmitter for Ericsson EDGE TDMA chipsets. Design included waveform generation, interpolation filers and sigma delta digital to analog converters. Owned synthesis flow and simulated using Modelsim. Used Matlab for design tradeoffs and filter design.Handled many system aspects related to the transmitter including Error Vector Magnitude verification, analog filter design, and high-level architecture of the block.FPGA logic to distribute voice and data to four AMPS/DAMPS radio transceivers received over a T1 link including patented technique to calibrate out transmission delays