Ranjith M Email & Phone Number

As an RTL Engineer with nearly 3 years of hands-on experience, I specialize in the design, synthesis, and implementation of digital systems. My expertise covers a range of hardware description languages (HDL), including Verilog, System Verilog, and VHDL. I have worked extensively on:> Top-level integration> Developing efficient RTL designs and verifying them through functional and timing simulations.> Skilled in designing and implementing industry-standard protocols such as AXI bus, UART, I2C, SPI, PCIe, Ethernet MAC, XGSPON.> Synthesis & ensuring designs meet timing constraints.> Experienced in Testing, debugging using Integrated Logic Analyzer (ILA) .> python, Perl, shell scripting for testing.> Static Timing Analysis > knowledge on RISC V architecture

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  Rtl Design Engineer

  Vvdn Technologies

  Mar 2022 - Present - Kochi, Kerala, India

  RTL Engineer with nearly 3 years of experience in design, synthesis, and implementation of digital systems. Proficient in Verilog, SystemVerilog, and VHDL, with expertise in top-level integration, protocol design (AXI, UART, I2C, SPI, PCIe, Ethernet MAC, XGSPON), and hardware testing. Skilled in functional and timing simulations, static timing analysis (STA), and hardware debugging using Integrated Logic Analyzer (ILA). Adept at delivering high-performance designs with a focus on timing closure and verification.

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  Nandha Engineering College - Company

  Cgpa: 7.98