Ravin Chourikar Email & Phone Number

Bengaluru, Karnataka, India

The position of PMTS involved working as a Technical Lead on several SoCs in domains including Security, Energy metering, Micro controllers, Industrial and Automobile. My responsibilities as Technical lead on various SoCs included working with cross functional teams spread geographically: - Specification generation based on business inputs- Architecture/Micro-Architecture - RTL Design Implementation & Verification - Synthesis- PnR interactions for optimal placement… Show more The position of PMTS involved working as a Technical Lead on several SoCs in domains including Security, Energy metering, Micro controllers, Industrial and Automobile. My responsibilities as Technical lead on various SoCs included working with cross functional teams spread geographically: - Specification generation based on business inputs- Architecture/Micro-Architecture - RTL Design Implementation & Verification - Synthesis- PnR interactions for optimal placement for power and Mixed Signal flow- Timing Analysis with sign-off- Interactions with Analog team including schematic generation- Interactions with layout engineer for DRC, LVS sign-off- Tapeout Interactions with Foundary including GDS database handover, flash integration etc to initiate SoC manufacture- Silicon Characterization for Analog and Digital dataset parameters- Silicon debug including bench setup and flow definition - Test team interaction for Silicon Characterization, Production program sign-off with 6 sigma Guaranteed By Design (GBD) - Firmware inputs to support customer Design-in of the SoCs Show less

I was with the Micro-controller Business Unit. During my role as a Senior Design Engineer I worked on several IPs a few key ones are listed below. This included design and verification responsibilities at block and chip-top level including Mixed Signal verification. - AES Engine: A low foot print, low power AES engine was required for secure micro-controller products. I delivered on the requirements which involved translating the FIPS Standard AES document into suitable… Show more I was with the Micro-controller Business Unit. During my role as a Senior Design Engineer I worked on several IPs a few key ones are listed below. This included design and verification responsibilities at block and chip-top level including Mixed Signal verification. - AES Engine: A low foot print, low power AES engine was required for secure micro-controller products. I delivered on the requirements which involved translating the FIPS Standard AES document into suitable micro-architecture with RTL implementation and proving that it's bug-free by passing billions of test-cases on the IP. The IP includes interface to Maxim MAXQ TRaNsport Network Interface as well as APB interface. The AES IP is work horse of many Maxim secure products.- SHA IP: I was part of the team that delivered the micro-Architecture for the SHA IP.I also worked on several other IPs/products developing, verifying various IPs such as Pulse Width Modulation Timers, Tripe DES,MAA, USB, ISO-UART, LIN, 1-wire, ADC decimating digital filers etc. for ARM as well as MAXQ processor. Show less

Mtech, Vlsi Design Tools & Technology (Vdtt)

Bachelor Of Engineering (Be), Electrical And Electronics Engineering

High Secondary School Certificate, Science

Matriculation, Elementary, Secondary And High School Education