Raymond Zeng Email & Phone Number

2655 Seely Avenue, San Jose, Ca

Develop and maintain Palladium verification platform. Palladium is a high performance computing system. Simulation, acceleration and emulation are integrated in a unified verification environment. My responsibility includes the development of Dynamic Power Analysis(DPA), FullVision computation(fvCompute), Common Power Format(CPF), Unified Power Format(UPF) features, Dynamic Register Transfer Level(DRTL US Patent 10,198,539), State Description Language(SDL), performance optimization for distributed computation system and next generation of emulation platform.

Xiamen, Fujian, China

Maintain and enhance Verdi/Novas. Take charge of trace engine and related GUI of Temporal Flow View., including trace engine’s architecture and performance optimization. Develop debugging solution for low power design that integrates logic design with Common Power Format (CPF) or Unified Power Format(UPF).