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Revanth Chakilam Email & Phone Number

Layout Design and CAD and Methodology Engineer at Ampere
Location: Portland, Oregon, United States 6 work roles 2 schools
1 work email found @invecas.com LinkedIn matched
✓ Verified May 2026 4 data sources Profile completeness 86%

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Current company
Ampere
Role
Layout Design and CAD and Methodology Engineer
Location
Portland, Oregon, United States
Company size
1359 employees

Who is Revanth Chakilam? Overview

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Quick answer

Revanth Chakilam is listed as Layout Design and CAD and Methodology Engineer at Ampere, a company with 1359 employees, based in Portland, Oregon, United States. AeroLeads shows a work email signal at invecas.com and a matched LinkedIn profile for Revanth Chakilam.

Revanth Chakilam previously worked as CAD/Methodology Engineer at Ampere and Physical Design/CAD Intern at Ampere. Revanth Chakilam holds Master Of Science - Ms, Electrical And Computer Engineering, First Class With Distinction from Portland State University.

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Email format at Ampere

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{first}.{last}@invecas.com
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Profile bio

About Revanth Chakilam

Experience in Physical design of CPU which involves ASIC design flow activities like Floor planning, Synthesis, Placement, CTS and Routing.Exposure on timing convergence strategies of high speed blocks through industry standard sign-off EDA tools.Proficiency in Physical Design Verification checks such as DRC, LVS. Experience in Analog & Mixed Signal IC Layout Design on various lower technology nodes.Exposure to Industry standard EDA tools like Cadence Virtuoso, Cadence Innovus, Cadence Genus, Siemens Calibre, PT, Synopsys DC and Synopsys Custom Compiler.Good working knowledge of Linux OS, Shell scripts, TCL Programming.Exposure in Layout Automation Scripting language like Cadence SKILL.

Current workplace

Revanth Chakilam's current company

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Ampere
Ampere
Layout Design and CAD and Methodology Engineer
Portland, OR, US
Website
amperecomputing.com
Employees
1359
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Company profile
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6 roles

Revanth Chakilam work experience

A career timeline built from the work history available for this profile.

Layout Design And Cad And Methodology Engineer

Ampere

Portland, OR, US

Cad/Methodology Engineer

Current
Ampere

Portland, Oregon, United States

Jul 2023 - Present

Physical Design/Cad Intern

Ampere

Portland, Oregon, United States

  • Responsible for Physical Design of high speed block, which includes ASIC design flow such as Floor planning, Synthesis and PNR.
  • Involved in the timing convergence strategies to meet timing requirements through standard Sign off tools.
  • Worked on Physical Verification checks of my design.
  • Worked on basic automation tasks using Tcl.
Aug 2022 - Jun 2023

Ams Layout Design Engineer

Invecas

Hyderabad, Telangana, India

Nov 2019 - Dec 2021

Analog Layout Trainee

Veda Iit

Hyderabad, Telangana, India

Worked on Analog & Mixed Signal IC Layout Design in various Lower Technology Nodes which includes, 14nm FinFet Technology.22nm FDSOI Technology28nm MOSFET Technology.I have been exposed to Industry standard EDA tools like Cadence' Virtuoso, Mentor Graphics' Calibre.As an Analog Layout Trainee, I have developed layouts ranging from basic blocks including.

May 2019 - Oct 2019

Engineer

Tata Elxsi

Bengaluru, Karnataka, India

Nov 2018 - Apr 2019
Team & coworkers

Colleagues at Ampere

Other employees you can reach at amperecomputing.com. View company contacts for 1359 employees →

MJ Madhavi Joshi Madhavi Joshi Colleague at Ampere Bikaner, Rajasthan, India, India View → JF Julie Falender Julie Falender Colleague at Ampere Portland, Oregon, United States, United States View → AB Anwesh Bhat Anwesh Bhat Colleague at Ampere Pune, Maharashtra, India, India View → SK Shirish Kulkarni Shirish Kulkarni Colleague at Ampere Hyderabad, Telangana, India, India View → DD Deepak Dwivedi Deepak Dwivedi Colleague at Ampere Bengaluru, Karnataka, India, India View → HT Harry Teuteule Harry Teuteule Colleague at Ampere St.-Maximin-la-Ste.-Baume, Provence-Alpes-Côte d'Azur, France, France View → CS Chris Swanson Chris Swanson Colleague at Ampere Berkeley, California, United States, United States View → AK Apurva Kokate Apurva Kokate Colleague at Ampere Pune, Maharashtra, India, India View → MS Mary Spradling Mary Spradling Colleague at Ampere Morrisville, North Carolina, United States, United States View → TK Tanvir Kaur Tanvir Kaur Colleague at Ampere San Jose, California, United States, United States View →
2 education records

Revanth Chakilam education

Master Of Science - Ms, Electrical And Computer Engineering, First Class With Distinction

Portland State University

Graduate Student with Specialization in Digital IC Design

FAQ

Frequently asked questions about Revanth Chakilam

Quick answers generated from the profile data available on this page.

What company does Revanth Chakilam work for?

Revanth Chakilam works for Ampere.

What is Revanth Chakilam's role at Ampere?

Revanth Chakilam is listed as Layout Design and CAD and Methodology Engineer at Ampere.

What is Revanth Chakilam's email address?

AeroLeads has found 1 work email signal at @invecas.com for Revanth Chakilam at Ampere.

Where is Revanth Chakilam based?

Revanth Chakilam is based in Portland, Oregon, United States while working with Ampere.

What companies has Revanth Chakilam worked for?

Revanth Chakilam has worked for Ampere, Invecas, Veda Iit, and Tata Elxsi.

Who are Revanth Chakilam's colleagues at Ampere?

Revanth Chakilam's colleagues at Ampere include Madhavi Joshi, Julie Falender, Anwesh Bhat, Shirish Kulkarni, and Deepak Dwivedi.

How can I contact Revanth Chakilam?

You can use AeroLeads to view verified contact signals for Revanth Chakilam at Ampere, including work email, phone, and LinkedIn data when available.

What schools did Revanth Chakilam attend?

Revanth Chakilam holds Master Of Science - Ms, Electrical And Computer Engineering, First Class With Distinction from Portland State University.

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