Ritesh K Email and Phone Number
Low power Physical Implementation for mobile processor chips, worked for first in industry for 7nm, 10nm node to make a high speed server implementation. Worked for High performance server implementation from RTL to GDS, with complete physical, timing & electrical sign-off.
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Principal EngineerTsmc Jul 2015 - PresentHsinchu County/City, TaiwanWorking on Physical Implementation for 7nm & 10nm node. -
Senior Technical Consultant For Low Power Physical ImplementationSynapse Design Inc. Nov 2012 - Jun 2015BangaloreWorked for Low power ASIC implementation for 28nm & 20nm for mobile processor chips -
Senior Staff EngineerIbm May 2010 - Oct 2012BangaloreWorked for Physical implementation for P6 processor -
Design EngineerAmd Apr 2007 - May 2010I am responsible for high end microprocessor design & physical implementation. -
Design EngineerTexas Instruments Jan 2004 - Mar 2007Design ENgineer
Ritesh K Education Details
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Microelectonics -
Electronics And Communications Engineering
Frequently Asked Questions about Ritesh K
What company does Ritesh K work for?
Ritesh K works for Tsmc
What is Ritesh K's role at the current company?
Ritesh K's current role is Master's degree at Birla Institute of Technology and Science, Pilani.
What schools did Ritesh K attend?
Ritesh K attended Birla Institute Of Technology And Science, Pilani, Babasaheb Bhimrao Ambedkar University.
Who are Ritesh K's colleagues?
Ritesh K's colleagues are 葉佩蓉, Evan Chen, Ming-Hsien Lin, 姚佑達, Scott Chen, 林榮忠, 葉俊宏.
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