Rob Rydberg Email & Phone Number

Redmond, Washington, United States

Engineering Systems Manager for the Azure Boost FPGA program supporting the network and storage acceleration teams. Responsible for building the team, establishing KPIs and processes, engaging with partner teams, and vendors. I organized the ES team across three pillars: 1) Build and Automation ◊ Chip-level and role-level DV and synthesis testing ◊ Multi-role FPGA build system across multiple project phases & FPGA vendors ◊ Integration with SW teams for system testing ◊ Automated release notes & manifest for multi-role FPGA builds ◊ Build metrics collection, analysis, and reporting 2) Test Labs ◊ Support lab needs across multiple teams in Azure Core Computer & Host ◊ Built a ticketing system ◊ Trained lab personnel on setup for PCIe analyzer on Azure host machines: analyzer setup typically ready for engineers within 4 business hours (24 hour SLA) ◊ Supported automated network and storage acceleration pre-deployment testing ◊ Kept labs in sync with the datacenter deployments ◊ Managed budget for space, lab crew, and build out 3) Hardware Engineering Center of Excellence ◊ Core RTL library; base RTL library for multi-vendor, multi-architecture library for use by the role teams ◊ Common RTL library; library for IP shared between multiple roles ◊ Physical Design; timing closure, resource reduction, & power reductionHigh-Level Synthesis; trail-blazing HLS adoption into existing designs

Redmond, Washington

FPGA development manager for the Storage Acceleration engine for Azure Boost • Deployed two FPGA-based HW projects into Azure ◊ The initial GA deployment completed without rollback and lived for more than 16 months before the first required update • Deployed the first NVMe controller attachable directly to guest VMs ◊ Led effort to triple the potential bandwidth ◊ Led effort to quadruple the number of supported VFs and vCPUs • Coordinated HW development effort across three teams and geographies • Led the Redmond HW team through the multi-year COVID-19 pandemic isolation ◊ Kept morale up with virtual events and eventual off-site meet-ups ◊ Made space for team members to be people ◊ Allowed my team to see my struggles to show it was okay ◊ Grew the team with automation and additional developers ◊ Adapted processes to support 100% WFHAdapted lab setups for no-touch in-lab HW testing

Bellevue, Wa

Developed an FPGA-based VR system architecture, allowing for a tethered or untethered VR experience, to make feature and tracking research more cost-effective, while enabling a faster path to productizationStarted a strategic partnership with the intent of creating a custom or semi-custom FPGA targeting VR and other high-resolution, high-frame rate productsCreated a patented sensor scheduling scheme (combined HDL and FW) to save 30-40% of sensor power consumption while actively trackingDiscussed and refined hardware accelerated video encoding solutions for real-time streaming of high-resolution videoRefined watchman/lighthouse tracking HDL, packing additional features into a 90% full FPGA. Wrote the accompanying firmware to best utilize the new HDL features.

Bothell, Wa

Lead FPGA engineer & digital architect on the T400L, the initial time-domain protection relay for SEL.Responsible for leading the development of digital architecture (FPGAs) across new and existing platforms for highly reliable power systems control equipment.Frequently brought into firmware projects to implement or review key features on time sensitive projects.Involved in training and mentoring new hires and new team members.Led company-wide efforts on FPGA fault tolerance and Single Event Effect mitigation strategies.

Greater Seattle Area

Taught a senior level embedded systems course in the Electrical and Computer Engineering Department. Designed the course to be project-based, using an FPGA as a development platform. Students learned how to turn an FPGA into a custom microcontroller, using FPGA tools, vendor provided IP and writing custom IP. They then wrote the software to drive their custom micro-controller, learning about the flexibility of FPGAs for systems development and had an introduction to real-time and embedded operating systems.

Pullman, Wa

Taught the following courses:Introduction to Computer ScienceMicroprocessorsEE Senior DesignSoftware EngineeringVLSI DesignWaveguides & Antenna Theory

Boise, Idaho Area

Product Engineering -- CMOS Imaging

Albuquerque, New Mexico Area

ASIC/SoC Design Group

Albuquerque, New Mexico Area

ASIC/SoC Design Group

Doctor Of Philosophy - Phd, Computer & Electrical Engineering

Activities and Societies: ACM, IEEE, Graduate & Professional Student Association, Wind Symphony, Symphony Orchestra, Low Brass.

Master Of Science - Ms, Electrical Engineering

Activities and Societies: IEEE, Graduate & Professional Student Association, Wind Symphony, Symphony Orchestra, Low Brass Studio

Bachelor Of Science - Bs (Double Major), Computer Engineering & Computer Science

Activities and Societies: Mu Phi Epsilon, IEEE, ACM, University Wind Ensemble, University Symphony Orchestra, Hinderlie Hall CouncilMusic.