Robert Haller Email & Phone Number

Morrisville, Nc, Us

Signal Integrity Group Lead for new combined company immediately becomes a networking industry leader with more than 12,000 customers.Corporate SI guru with history of solving toughest customer problems. DESIGNCON Technical Program Committee (TPC) member for 16 years and track co-chair for SI premier conference . Stong technical and verbal/written communication skills. Mentors senior and junior engineers. Experience and proficient working in ODM/JDM model. Gillette Stadium WI-FI coach.

San Jose, Ca, Us

Hardware Architect and Group Leader for SI/PI for secure network company. Responsibilities include system architecture, design and debug, interface with ASIC, logic and software engineering, hardware technology selection, verification and implementation. System level lab debug of the toughest issues utilizing high speed Scope, Spectrum analyzer, TDR and VNA. Expert user of HFSS, SIWave, HSPICE, SiSoft's QCD, QSI, IBIS-AMI, Mentor and Cadence Cad Tools. Responsibilities include concieve, designing and debug next generation high speed networks, backplanes and power distribution. SI for ASIC's, ASIC package design, High Speed Channel Design, 6.25G,10G,25G and 100G, PCIE, SPI4.2, DDR4,3,2,1 I2C, USB, IEE802.3 and interfacing with firmware, mechanical, manufacturing, GTAC and customers. Extensive experience with DUNE and Broadcom Chipsets and tuning SERDES.

Sudbury, Massachusetts, Us

Team leader of Signal Integrity Software’s consulting team. Engaged in analyzing and verifying customer designs for SI and timing in both simulation and the lab. Work with potential and existing customer generating schedules, deliverables, tasks, and quotes. Perform accurate 2D and 3D modeling of connectors, packages, boards, and backplanes using Ansoft’s Q3D, HFSS and SiWave. Setup, debug and run complex simulation environments and generate industry design kits for high-speed parallel and multi-Gbs Links including SATA, PCI-Express, DDR2, and PCIX. Work in the lab with high-speed test equipment to correlate simulations with bench measurement. Engage SiSoft software developers conceiving, specifying and testing signal integrity software (SiAuditor). Generate and perform signal integrity and timing training at major companies. Debug, verify and utilize SPICE2IBIS. IBIS Quality Committee Chairman. Conceive, write, present and participate in industry panels, conferences, and papers.

Lead Signal integrity engineer for storage system startup. Responsibilities include process, technology, and cad tool selection, verification and implementation. Expert user of SPECCTRAQUEST (SI analysis), BLAST (static timing), and HSPICE. Evaluated, purchased and utilized high-speed scopes (electrical and optical), and TDR’s. Responsibilities also included managing PCB layout group and, hardware cad tools. Experience with high-speed processors, FPGA’s, memory design, Fiber Channel, and Gigabit ethernet.

Houston, Texas, Us

Lead signal integrity engineer and CAD tool specialist for enterprise class server. Responsibilities include technology selection, cad tool and process selection, verification and implementation. Signal integrity responsibility for server motherboard, interconnect and test vehicles. Perform module level timing and signal integrity verification of backplanes and modules on and across all connector boundaries. Perform evaluations between internal tools and External tools (HSPICE, SPECCTRAQUEST, XTK, ICX/TAU, MOTIVE). Generate behavioral I/O Models and verification for passives, discrete components and ASIC’s. Responsible for lossy line model generation and verification to bench using boundary element field solver. Setup and performed complex HSPICE simulations. Performed correlation of models and waveforms to bench. Experienced with HP and Tektronix scopes, pulse generators, test equipment and data acquisition software. MCA3 10K (Bipolar) gatearray design, full custom chip design, co-designed SI Chip test vehicle.

Msee, Electrical Engineering

Bsee, Electrical Engineering