Robert Kleijnen Email & Phone Number

Leuven, Vlaanderen, België

Jülich

Neuromorphic Computing: SoC conceptual approaches enabling natural density connectivity

Veldhoven

Master Thesis ProjectTitle: "Sub-10nm scaling of FinFET-based high-density SRAMs"Research focus:• Reverse Engineering: Extraction of the technical and physical design of SRAM systems of different foundries using SEM and TEM images made during a product teardown.• Investigation of the functionallity, layout and physical implementation and production process of SRAM and the corresponding limitations for the scaling due to technological or physical limitations.• Analysis… Show more Master Thesis ProjectTitle: "Sub-10nm scaling of FinFET-based high-density SRAMs"Research focus:• Reverse Engineering: Extraction of the technical and physical design of SRAM systems of different foundries using SEM and TEM images made during a product teardown.• Investigation of the functionallity, layout and physical implementation and production process of SRAM and the corresponding limitations for the scaling due to technological or physical limitations.• Analysis of current scaling trends due to the shrinking transistor size and extrapolation of these trend in order to predict future changes to the SRAM design or technology.• Evaluation of the conventional SRAM metrics and determination of the correlation between these metrics and the dynamic performance of the SRAM cells using Cadence Spectre and SPICE.• Simulating SRAM cells for circumstances corresponding with the scaling trends in order to determine the limitations of the current technologies and implementations Show less

'S-Gravenvoeren

Veldhoven

Official Internship description:Investigate the challenges and limitations concerning the scaling of DRAM memory systems and in particular, the voltage sense amplifier.Main Task: Investigate the challenges concerning the scaling of DRAM memory systems and in particular, the voltage sense amplifier and help develop a predictive roadmap for DRAM memory and specify possible user cases for ASML products in the DRAM production process. Main activities:• Reverse… Show more Official Internship description:Investigate the challenges and limitations concerning the scaling of DRAM memory systems and in particular, the voltage sense amplifier.Main Task: Investigate the challenges concerning the scaling of DRAM memory systems and in particular, the voltage sense amplifier and help develop a predictive roadmap for DRAM memory and specify possible user cases for ASML products in the DRAM production process. Main activities:• Reverse Engineering: Extract the technical and physical design of the DRAM memory chips from different manufactures using SEM and TEM images from a product teardown.• Research the functionality, layout, physical implementation and production process of DRAM and the occurring limitations of scaling due to technological or physical limits.• Analysis of recent designs to predict possible future changes to the DRAM design, and especially the voltage sense amplifier, to overcome the scaling limits.• Reasearch the possibilities to increase reliability of DRAM systems with ECC (Error Correction Code), either system level or on Chip. Show less

Kreisfreie Stadt Aachen Area, Germany

● Implementing a Fast Fourier Transform-Macro in a 28-nm Technology using standard cell synthesis of a parameterized and modular description in the hardware description language Verilog and analysing the design and the influence of the different parameters on time-, area- and power-constraints.● Estimate the power consumption of designs using different approaches and tools and evaluate the approaches and tools in regards to duration, accuracy and reliability

Kreisfreie Stadt Aachen Area, Germany

Tutoring first semester students during the “MATLAB meets LEGO Mindstorms” project

Master Of Science (M.Sc.), Electrical Engineering And Information Technology

Major: Micro- and Nanoelectronics Master Thesis: “Sub-10nm scaling of FinFET-based high-density SRAMs” Laboratory courses: VLSI-Design.

Bachelor Of Science (B.Sc.), Electrical Engineering And Information Technology

Major: Micro- and Nanoelectronics Bachelor Thesis: "Analysis of latency-optimized FFT-circuits for area- and energy-efficient digital.

Gymnasium

Activities and Societies: Exchange with Iași (Romania), Exchange with Lecce (Italy) Comparable to a university-preparatory education.