Rob Pelt Email & Phone Number

Santa Clara, California, US

Lead chiplet architect focused on next generation AMD products. Heavily involved in UCIe.

Austin, TX, US

Short time at Mythic working on architecture for flash-based analog AI engine. Evaluation of existing architecture and proposals for improvement.

Kista, Stockholm, SE

CPU subsystem architecture for 5G ASICs. Includes CPU integration, high-performance interconnect, debug.Performance architecture for ARM-based SoCs.Lead hardware ASIC security architect for next generation 5G ASICs.

Hillsboro, OR, US

Research on next-generation embedded programmable accelerators.Leading a team of researchers implementing programmable architecture exploration tools. Areas of responsibility include: - Performance extraction and simulation methodologies - CAD software development for new programmable architectures. - Exploring Machine Learning techniques for programmable.

Santa Clara, California, US

Lead architect and product manager for FPGA-based acceleration architectures that are coupled with Intel x86 devices. Creating solutions that span low-cost (Atom) and high-end (Xeon) acceleration needs. Responsible for product definition and technical solution. Technical leader for hardware, software, and compiler development.

Santa Clara, California, US

Responsible for ARM-based SoC FPGA product roadmap. Interface with customers to gather system requirements. Areas of responsibility include: SoC performance, power, and features Security features and implementation Functional Safety requirements

Lead Architect of FPGA configuration solution for Stratix 10 devices. Responsibilities include multiprocessor systems (100's of independent microprocessors); secure data transfers, NOC interconnect; and various high-performance subsystems. System architecture for next-generation SoC and FPGA. Areas of expertise: FPGA architecture and implementation. SoC.

San Jose, CA, US

SoC architecture and development using ARM1176 and Cortex-A9Next generation FPGA architecture (45nm, 32nm, and beyond)FPGA performance evaluation and enhancementPower reduction techniquesWireless, Video, and general DSP development

Santa Clara, CA, US

System engineering of wireless, video, and communications designs on Tabula's FPGA technology.

Product Planning for 65nm FPGA, DSP capabilities, and System Design SoftwareSystem architecture for customers using FPGA for DSP implementations.

US

Architecture of reconfigurable processor. Wireless, Video, and DSP algorithms.

Many simultaneous clients. Areas include FPGA design, DSP design, System Architecture, Embedded Software

St Petersburg, FL, US

FPGA design for SONET, ATM, T1. Architected, designed, tested, and delivered product.

Chicago, Illinois, US

Hardware and software design for Iridium handsets.

Msee, Communications, Digital Signal Processing

Bsee, Analog/Digital Design

High School