Roger Stevens Email & Phone Number

Austin, Texas Area

Albuquerque, New Mexico Area

• Scoping, scheduling, reviewing, and tracking work for layout team • Training coordinator • Top level floor planning • Top level and block level custom mixed-signal layout • work in the following process IBM 32nm, IBM 45nm, IBM 130 and internal process • Library development / methodology co-owner of PDK • Manage PCell /schematic symbol development • Manage skill development Winner of the Innovative Technologist award Clearance: DOE Q

Utica, Ms

■ Managed performance, sales and training of employees. Created sustainable accountability and motivation with employees by setting up reward programs including cash bonuses and paid time off. ■ Financial management ; developed forecast of revenue, expenditure and profit. Wrote viable business plans for 10 years that led to sound business decisions and consistent profits.■ Managed day-to-day business operations from sale of services to project completion as a provider of engineering services for major US semiconductor companies.

Ridgeland, Ms 39157

■ Managed multiple teams of lead layout designers around the globe • Recruited all contract and permanent layout hires • Tracked all projects being designed by the layout team to ensure that all projects completed on or before deadlines • Perform yearly reviews for layout team, assigned senior layout engineers in mentoring program • Ensured proper layout methodology and revision controls were practiced • Worked with other layout managers to ensure a constant methodology though out the company■ Created a shuttle program to allow multi groups / projects on the same mask set • Saved 3 million dollars in mask cost the first year • Directed the fab on the process of each wafer to ensure proper processing • Worked with mask prep to ensure that the wafer reticale floor plan was done correctly i.e. designs were placed where they did not cause density issues that would affect processing • Supervised the creation of a web based application to allow customers easy usage and tracking of their designs■ Drove the development of bonding checking software • Allowed the layout designer to fix possible bonding issues before silicon • Faster floor planning■ Created analog-mixed signal layout designs • Top level and block level floorplans • Processes worked TSMC .18um and internal .35 BiCMOS, and 90nm • Types of projects sensors, automotive and RF

Ridgeland, Ms 38157

■ Grew a layout design team from two to fifteen designers in less than two years while in a region that did not have a strong engineering base■ Developed Analog mixed signal flow to ensure digital blocks inserted in analog chips without issues■ Top level mixed signal layout and block level analog layout■ Recruited, hired, trained and disciplined layout designer■ Created SOP’s to insure best practices were followed■ Digital backend design using Cadence SE • Block floorplanning • cell placement and routing • timing closure / verification ■ Created analog-mixed signal layout designs • Top level and block level floorplans • Processes worked in to many to list • Types of projects audio, RF and Power Management

Raymond, Ms

Taught three courses: Basic Unix Basic Cadence VirtuosoBasic mix signal layout, which included device matching concepts, special routes (shielding, coaxial, etc.) , LVS, DRC, and block floor planning.

Block level layout of custom analog layout, Standard Bipolar, BiCMOS, CMOS

Ft Mcpherson

32D telecommunications Tech., responsible for all data and voice lines going into the base.

Bachelor Of Applied Science (B.A.Sc.), Eet Minor In Cet

Associate Of Science (A.S.), Eet