Ron Kedem Email & Phone Number

Copenhagen, Capital Region, Denmark

Led and hands-on developed Networking System ASIC device IPs, with complete responsibility from concept to signoff, including architecture, micro-architecture, design implementation, timing exploration and IP assimilation in both SoC and Networking (Ethernet Switching) ASIC devices.Led and hands-on developed Time Synchronization sub-system IPs with focus on Time Stamping and Time Application IPs supporting Precision Time Protocols, principally PTP v1/v2 1588.Acted as the focal point of Time Synchronization sub-system IPs and discipline in both the Networking and SoC divisions.Developed several multi discipline IPs: Multi-channel RX / TX bridges and LED Controller.Issued several patents related to the owned IPs.Collaborated extensively with Product Definition and Architecture group members.Cooperated with and supported RnD groups: Chip Frontend, Physical Design (Backend), RTL/Formal Verification, Chip Validation, SW, HW and Customer Support.

Acted as the principal designer of the DRAM memory controller IP of the company, embedded in both SoC Embedded Processors Computing and Networking divisions.Led and hands-on developed a memory access IP from concept to signoff, assimilated in the DRAM memory controller IP, aimed at accelerating its performance for the purpose of DDR3 to DDR4 technology upgrade. Collaborated with Product Definition and Architecture group members.Registered a patent related to the memory access IP micro-architecture.

Managed the frontend (design and verification) and post-silicon activities of a flagship, highly innovated high-end ASIC SoC device program throughout 4 ASIC device projects. The SoC device integrated several cutting-edge technologies and IPs including ARM CPU, GPU (graphic processor), VPU (Video processor) and LCD controller.Led and managed a multisite team of 10 engineers composed of several teams in the company’s Israeli and US sites.Prepared verification strategies and design plans, challenged engineering plans and monitored execution, schedule and progress by the team members in both the Israeli and US sites, including on-site collaboration in the US site.Undertook leaders’ course.

Co-Designer of several SoC ASIC IP blocks. Inbound collaboration with product definition architects for planning the micro-architecture of the blocks.Responsible for full chip design and assimilation in several SoC ASIC devices.Responsible for backend closure of several full chip macros in several SoC ASIC projects.

Led DRAM controller IP verification team of 2 engineers, responsible for preparing verification strategies and plans and monitor execution schedule and progress.Responsible for assimilating the IP in full chip level of several SoC ASIC devices.

Modelled the functionality of external protocols in RTL blocks’ simulation environments, using Verilog.Modelled the functionality of several different RTL blocks using an internal tool written in C++. The tool was used for verifying the blocks’ functionality.Responsible for assimilating the C++ model in full chip level in several different SoC devices.