Ron Kedem

Ron Kedem Email and Phone Number

IC Digital Design and Architecture Engineer at Comcores ApS @ Comcores ApS
lyngby, central jutland, denmark
Ron Kedem's Location
Copenhagen, Capital Region of Denmark, Denmark, Denmark
Ron Kedem's Contact Details

Ron Kedem personal email

n/a
About Ron Kedem

IC Engineer with 20+ years of in-depth experience in diverse VLSI development aspects, focused on micro-architecture, design, and architecture. Developed complex high performance micro-architectures and designs for leading edge SoC and Networking devices. Recently returned to Israel after a relocation and working period in Copenhagen, Denmark.

Ron Kedem's Current Company Details
Comcores ApS

Comcores Aps

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IC Digital Design and Architecture Engineer at Comcores ApS
lyngby, central jutland, denmark
Website:
comcores.com
Employees:
46
Ron Kedem Work Experience Details
  • Comcores Aps
    Ic Digital Design And Architecture Engineer
    Comcores Aps Nov 2022 - Present
    Copenhagen, Capital Region, Denmark
  • Xsight Labs Ltd
    Vlsi Asic Design And Micro-Architecture Engineer
    Xsight Labs Ltd Mar 2020 - Sep 2022
  • Marvell Technology
    Asic Ips Design, Micro-Architecture And Lead Engineer
    Marvell Technology Mar 2015 - Feb 2020
    Led and hands-on developed Networking System ASIC device IPs, with complete responsibility from concept to signoff, including architecture, micro-architecture, design implementation, timing exploration and IP assimilation in both SoC and Networking (Ethernet Switching) ASIC devices.Led and hands-on developed Time Synchronization sub-system IPs with focus on Time Stamping and Time Application IPs supporting Precision Time Protocols, principally PTP v1/v2 1588.Acted as the focal point of Time Synchronization sub-system IPs and discipline in both the Networking and SoC divisions.Developed several multi discipline IPs: Multi-channel RX / TX bridges and LED Controller.Issued several patents related to the owned IPs.Collaborated extensively with Product Definition and Architecture group members.Cooperated with and supported RnD groups: Chip Frontend, Physical Design (Backend), RTL/Formal Verification, Chip Validation, SW, HW and Customer Support.
  • Marvell Technology
    Staff Design Engineer – Soc Asic Ips Design And Micro-Architecture Engineer
    Marvell Technology Dec 2010 - Mar 2015
    Acted as the principal designer of the DRAM memory controller IP of the company, embedded in both SoC Embedded Processors Computing and Networking divisions.Led and hands-on developed a memory access IP from concept to signoff, assimilated in the DRAM memory controller IP, aimed at accelerating its performance for the purpose of DDR3 to DDR4 technology upgrade. Collaborated with Product Definition and Architecture group members.Registered a patent related to the memory access IP micro-architecture.
  • Marvell Technology
    Project Frontend And Post-Silicon Manager
    Marvell Technology Jan 2007 - Dec 2010
    Managed the frontend (design and verification) and post-silicon activities of a flagship, highly innovated high-end ASIC SoC device program throughout 4 ASIC device projects. The SoC device integrated several cutting-edge technologies and IPs including ARM CPU, GPU (graphic processor), VPU (Video processor) and LCD controller.Led and managed a multisite team of 10 engineers composed of several teams in the company’s Israeli and US sites.Prepared verification strategies and design plans, challenged engineering plans and monitored execution, schedule and progress by the team members in both the Israeli and US sites, including on-site collaboration in the US site.Undertook leaders’ course.
  • Marvell Technology
    Senior Design Engineer
    Marvell Technology Jul 2004 - Jan 2007
    Co-Designer of several SoC ASIC IP blocks. Inbound collaboration with product definition architects for planning the micro-architecture of the blocks.Responsible for full chip design and assimilation in several SoC ASIC devices.Responsible for backend closure of several full chip macros in several SoC ASIC projects.
  • Marvell Technology
    Verification Ip Team Leader
    Marvell Technology Jul 2002 - Jul 2004
    Led DRAM controller IP verification team of 2 engineers, responsible for preparing verification strategies and plans and monitor execution schedule and progress.Responsible for assimilating the IP in full chip level of several SoC ASIC devices.
  • Marvell Technology
    Verification Engineer
    Marvell Technology Jul 2000 - Jul 2002
    Modelled the functionality of external protocols in RTL blocks’ simulation environments, using Verilog.Modelled the functionality of several different RTL blocks using an internal tool written in C++. The tool was used for verifying the blocks’ functionality.Responsible for assimilating the C++ model in full chip level in several different SoC devices.

Ron Kedem Skills

Soc Asic Rtl Coding Rtl Design Verilog Vlsi Semiconductors Ic Debugging Functional Verification Embedded Systems Arm Logic Design Processors

Ron Kedem Education Details

Frequently Asked Questions about Ron Kedem

What company does Ron Kedem work for?

Ron Kedem works for Comcores Aps

What is Ron Kedem's role at the current company?

Ron Kedem's current role is IC Digital Design and Architecture Engineer at Comcores ApS.

What is Ron Kedem's email address?

Ron Kedem's email address is ro****@****ell.com

What schools did Ron Kedem attend?

Ron Kedem attended Tel Aviv University.

What skills is Ron Kedem known for?

Ron Kedem has skills like Soc, Asic, Rtl Coding, Rtl Design, Verilog, Vlsi, Semiconductors, Ic, Debugging, Functional Verification, Embedded Systems, Arm.

Who are Ron Kedem's colleagues?

Ron Kedem's colleagues are Iacob Larsen, Otto Westy Rasmussen, Szymon Grzybek, Kashif Virk, Anne Voss Winther, Piotr Koziuk, Mathias Bæk.

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