- Leading the team to deliver manufacturing test program for Edge Product, performing reject validation, yield analysis, vmin/fmax characterization, defect analysis to meeting defects per million goal of 500.- Initiated process improvements by implementing new workflows for debugging, eliminating hardware modification and Lauterbach Trace32 licensing.- Delivered critical engineering test framework for Silicon Power-On, which helped debug test content in-house, saving external tester-time and revenue of 18%.- Drove test time reduction experiments to achieve overall test time reduction of 13%.- Responsible for ensuring the testability and manufacturability of Integrated Chips from component feasibility stage through production ramp. - Worked on coverage debug and DFT verification to achieve 98% stuck-at and 90% at-speed coverage.- Developed and validated test-plans and methodologies to meet 500 DPM (Defects per million) goal.- Performed test characterization to cover manufacturing variations as well as temperature and voltage margining ensuring yield and reliability.

- Worked in the emulation environment (Veloce and Zebu) as a part of the Graphics System Validation Integration and Debug team, executing emulation and simulations on the graphics and un-core part of the processor.- Analyzed failures based on type, capturing waveform (fast-wave and full capture) and deep dive into waveform with understanding of design to debug and root cause a failure; involved in test-plan and content development.- Scripted in Perl to analyze architectural logs (of core and peripherals) to root cause the failure and coordinated with different teams across the organization to identify the underlying cause and find a fix for the bug.

Grade Assignments, Quizzes and Exams for : - Computer Organization and Assembly Language Programming- Circuits 1.- Object Oriented Programming and Data Structures- CSE 110 Principles of Programming in JAVA.- Principles of programming in C++.

Duties include:-Making custom layouts using micromagic for 40nm as well as 65nm technology for layers to be stacked in 3D ICs.-RTL to GDSII : using Encounter(Cadence) for automatic placement and routing of functional blocks containing ~50 standard cells.-Running DRC and LVS using Calibre on the blocks and rectifying to make them clean.-Parasitic Extraction(PEX) using Calibre for simulation purposes.-Generation of lef(Library Exchange Format) from the layout using micromagic, Cadence Abstract and Encounter.-lib(Library file using for timing constraints) generation using what if commands as well as scripting in Encounter.

Duties included:- Preparing logic and programming Allen Bradley PLC using Ladder Diagram and Functional Block Diagram using Rockwell Software.- Designing SCADA and collaborating it with the program for data acquisition and complete monitoring of the system.- Aiding in Panel designing using Autocad.- Making library for common applications such as Sequencing, Conveyor Logic, Coal/Ash handling, Fermentation and Alarm Generation.

- Internship to complete final year training and project development.- Understood various steps in development of an application using Microcontroller.- Developed final year project - Smart Propeller Display using RF communication.