Data Center Office of Technology Center Custom ASIC Group Managed team responsible for all Custom ASIC Group projects infrastructure and supplied support.and guidance to other Data Center Group teams for Engineering Compute resource management. Responsible for forecasting and managing Engineering Compute resources and maintaining Custom ASIC Group budgets. Managed EDA licensing forecasting and budget for Custom ASIC Group and Optane projects. Provided infrastructure support to Custom ASIC Group teams and other Data Center Group teams for compute and storage. Managed closure and cleanup of Optane project resources. Chaired Compute Allocation Council team for collaboration between multiple business units andengineering compute.

Data Center and AI Custom ASIC Group/DCG Silicon Development Group Managed budgets for multiple projects  Managed EDA licensing forecasting and budget for all projects. Supported projects with ION/Netbatch/Storage resource needs. Active support role of project execution relating to infrastructure needs. Managed DCG Silicon Development Group System Validation team’s FPGA and Zebu emulation resources. Responsible for emulation budget and allocation along with debug and support of FPGA lab technicians

Intel Foundry Group Managed budget and purchasing for Foundry design team for compute and storage. Managed design environment infrastructure and releases. Managed interactive, Netbatch compute resources and storage resources. Managed EDA licenses, budget, and purchases for design team.

Responsible for bringing up CAD environment for 0.18um power process. • Developed Mentor AMPLE programs to customize tools for designers needs.• Developed symbol/layout libraries for 0.18um design kit using Mentor Graphics.• Created PERL scripts to enhance methodology flow and process data for analysis both pre and post simulation.• Supported Synopsys synthesis and static timing for digital blocks.• Managed a help desk ticket system to track designer issues.• Implemented a queue system based on Sun Grid Engine and created a simulation farm based on Linux servers.• Acted as system administrator for Linux systems in three locations used by designers for running Mentor tools including replication of design data between locations.

• Responsible as team lead for timing team. Directed timing team to close timing on CPU chip for the Xbox360. Provided leadership and training to timing members to close timing on units/modules. Directly responsible for chip level (top level) timing (unit-to-unit paths) and closing all timing violations to meet tape-out.• Worked as unit timer responsible for closing all timing paths for PCIX unit.

•Responsible for managing front end design tasks for the CAD group. Design tasks spanned creation of RTL design through netlist transfer for APR and back annotation for timing analysis and simulation. Personally responsible for synthesis, static timing, and verilog simulation for entire design center. Provided advanced support to design teams for synthesis, simulation, static timing verification, and logic verification. Also responsible for defining design tool methodologies for design groups.•Implemented novel solution to complex design problem such as created Verilog PLI to combine flip-flops into multibit cells to reduce routing congestion and clock tree loading for a graphics rendering controller. This system used PLI C code to recognize clock and control logic that was in common and combining four flip-flops into a single 4-bit flip-flop.•Created delay calculation flow for full custom blocks. System uses third party tools (Arcadia and PathMill) and custom code using C and Perl for SDF back annotation to Verilog-XL. Evaluated tools, created specification, designed methodology, and created C and perl code to generate SDF.•Principally responsible for evaluation of new EDA tools and flows to improve design processes or address design problems. For example, Sente (RTL Power estimation) and Vera (logic verification).•Problem troubleshooter. Responsible for finding solutions to design methodology problems. Responsible for researching, developing, and implementing solutions to the design methodology by evaluating and supporting third party tools, in house tools, or creating tools.•Created synthesis and static timing scripts for ARM based design in TSMC technology. Responsible for timing closure of 150MHz design.•Performed synthesis and static timing for MCU peripheral blocks as design team member. Created synthesis scripts and designed synthesis flow to meet timing goals. Also created scan chains for a USB peripheral in addition to synthesis tasks.

• Supervisor for EDA tool support and library development for the company. All major commercial tools supported. Personally responsible for Valid, Verilog, and Synopsys (synthesis). • Provided pre/post customer support for synthesis and simulation by visiting customers for technology transfer and to provide support for synthesis and timing closure.