S P. Email & Phone Number

RF/Optoelectronics

• Principal Integration Engineer – Oct.2007 to Feb.2010
• Managed the technical aspects of transferring an R&D project into a high volume production line. Specific duties included monitoring electrical and line yields, performing the Failure Analysis on fall-outs, and.
• Developed Plating and Sputtering processes for Unifacial Solar Cells.* Optimized the sheet resistance, stress and adhesive properties of the films without affecting the overall bow of the cell, through Design of.
• Developed in-house titration procedures to monitor the composition of the Plating bath that resulted in a savings of $1200/- per month.
• Redesigned the wafer mask to add one more cell per wafer. A potential increase of $440/- per wafer.

• C4 and ILD Integration Engineer. – Feb.2004 to Oct.2006
• Resolved any outgoing quality issues as the primary liaison between the Fabrication facilities and Intel’s assembly sites in China, Malaysia, Philippines and Costa Rica. Chaired the world wide weekly meetings for the.
• Individually led diverse teams in designing experiments, drove root cause failure analysis of process excursions in Inter Layer Dielectrics (CVD and CDO), and, Controlled Collapse Chip Connect (C4) (Passivation, PI.
• Served as the technical authority for a diverse group of process engineers and ensured that process changes in the far back end segment of the factory were properly implemented based on statistical data, and the.
• Evaluation and implementation of SPARK (a new polyimide) on P1263 products. (7 different geometries and Packages) to save $ 2 million per quarter.
• Taught courses in Far Back End Processing to peers and new hires.

• Thin Films and Diffusion Process Engineer. – Aug. 1987 to Jan. 2001
• Developed and sustained processes in Thin Films and Diffusion, in the 100mm,150mm and 200mm fabs.
• Developed, characterized and implemented a SOG module into production.
• Characterized and implemented barrier metal schemes on the ENDURA, MRC and GENUS.
• Investigated the capacitance characteristics of several passivation dielectrics.
• Characterized and implemented PSG and BPSG process schemes into production for device shrinks.