S Shashank Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

ATPG activities, Coverage Analysis for meeting Stuck-At Fault Test-Coverage requirements, GLS, Vector Readiness, Post-Silicon Debug.

Bengaluru Area, India

Worked on Notiming Serial & Parallel Simulations bringup.Had fun working on Power Aware GLS for SOCs. Debugged and fixed power-up sequence issues from test vectors in pre-silicon stage & contributed towards a smoother post-silicon bring-up. Carried PAGLS on both UPF Based & CLP (Conformal low power) netlist based power-aware environments.Enabled TDF Based memory-writethrough test for high-speed memories : Pattern generation, simulation & silicon bring-up.Generated and verified PDF patterns (Path-Delay Fault-Model) for CPU Sub-system.ATPG and re-target scan-patterns for stuck-at faults for various blocksEnhanced IDDQ Process further by creating necessary automation, adding required documentation and proposing new checklists.Also, helped ramp up new POCs in team for a smooth bring up for their respective designs.

Bengaluru Area, India

Worked on entire SOC enabled IDDQ bring-up for SoCs of different tech-node during this role.Performed DRC checks, Constraint Validation and Vector Generation for the same using Mentor Tessent TK Tool.Verified the quality of different flavors of IDDQ vectors by Simulating them in Synopsys VCS tool.Had fun to be a part of Post-Silicon debug activities : My responsibility was to ensure vector fails only on defective device and not on a good device. Further worked on enabling vector for reliability & yield loss debug.Not to miss, was involved in Python Scripting to Automate some of the tasks during above activities.

Bachelor Of Engineering (Be), Electronics And Communication Engineering, Cgpa 9.14

Pcme, Pcme, 94.33%

Cgpa 10