Saket Sharma Email and Phone Number

Sr. Design Engineer, HUBS group

Data Converters, Delta Sigma A/D Converters

Important Assignments : Design of RC delay based Voltage Controlled Oscillator in 0.35 micron technology (offsite for client based in Switzerland) - Silicon ProvenDesign of charge-pump based Voltage Multiplier and limiter circuit for the purpose of EEPROM erase/write operations in 0.35 micron technology (offsite for client based in Switzerland) - Silicon ProvenDesign of 1 bit Sigma Delta Modulator (ADC) in TSMC 180 nm technology (onsite for client in UK) - Silicon ProvenDesign of Class AB Op Amp used as analog buffer for analog test signals in TSMC 180 nm technology (onsite for client in UK) - Silicon ProvenDesign of Prescaler circuit operating at 3.1 Ghz in TSMC 180 nm technology (onsite for client in UK) - Silicon ProvenDesign of RFIO pad operating at 1.4 Ghz maximizing output power and minimizing intermodulation distortion in TSMC 180 nm technology (onsite for client in UK) - Silicon ProvenComplete design implementation of Bandgap Reference Circuit in TSMC 180 nm technology (onsite for client in UK) - Silicon ProvenDesign of Current Reference circuit to supply current for the whole chip in TSMC 180 nm technology (onsite for client in, UK)Design of low noise OTA (onsite for client in Czech Republic)Design of Power on Reset circuit for ultra low power in-house Standard Cell LibraryDesign of Charge Pumps (negative as well as positive) for ultra low power in-house Standard Cell Library

Important Assignments : Responsible for Maintenance & Operation of Telecom SwitchUnderwent training of one year for the same

Important Assignments :Responsible for the complete design implementation of USB 2.0 Transceiver PHY in ST's proprietary 130 nm technology. (Silicon proven)Designed PVT compensation circuit, Low-Full Speed Driver and Voltage/Current protection blocks including layouts from scratch.Implemented Suspend Mode current consumption of less than 1 micro amp.Improved design of Envelope Detector, High-Speed Differential Receiver, and Single-Ended Low/Full Speed Receiver after top level PLS showed failures in certain process-temperature corners.Design of 8 bit SAR ADC in IBM 90 nm technologyDesign of Folded Cascode OTA in IBM 90 nm technology