Asic Digital Design Intern
Current- Designed and did micro-architecture on a module to interface with an external IP that would supersede and add functionality on top of existing modules- Used and got familiar the Synopsis suite of tools VCS, Spyglass Lint, and Spyglass cdc, DVE- Ran and cleaning Lint errors on a large block using RTL changes and waivers- Ran and fixed CDC errors on a large block, learned about abstracting IP for use in CDC, writing constraints- Learned about the ASIC flow for chip design