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Business DevelopmentSoftware ConsultancyDevelopment of web based Applications

Define and design verification component for Genesis Product line.Suggested OVM usage. Presented OVM methodology.

Worked as Manager/Project/Team Lead/Individual Contributor.NCSIM : RTL simulator for VHDL/Verilog/Mixed design simulation with different parts like parser, code generator, elaborator and simulator engine.Manager for half of ncsim product change requests (bugs).Attended PSL working group committee meetings.Member of training program for new hires (VHDL, different parts of ncsim).Lead RCA analysis effort in the team.All kind of bug fixes and customer… Show more Worked as Manager/Project/Team Lead/Individual Contributor.NCSIM : RTL simulator for VHDL/Verilog/Mixed design simulation with different parts like parser, code generator, elaborator and simulator engine.Manager for half of ncsim product change requests (bugs).Attended PSL working group committee meetings.Member of training program for new hires (VHDL, different parts of ncsim).Lead RCA analysis effort in the team.All kind of bug fixes and customer support.Lead/Worked in areas like PSL/SVA assertions, SDF, Vital, VCD, EVCD, TCL, vhdl93, Solaris port support, re-architect driving/effective value phase of elaborator etc.ANALOG ARTIST: A market leader product providing Digital/Analog/Mixed Design Simulation environment for IC design.Owned hspiceD netlister integrationSIP related enhancement work in ADEPlanning/tracking new release milestonesQt based new widget development and supportSYNERGY: Synthesis tool. Bug fixing and enhancement support work. Show less

Worked as individual contributorDeveloped New toolsBlockarray : auto place and route utility for arraging blocks in row or column fashion for SOG/RAMLIB matrix.Preplace : preplacement utility for blocks, cannot occupy areas for SOG/RAMLIB matrix. Useful in floor-planning activity and detecting overlaps/out of matrix kind of checks.Sharp : setup/hold timing analysis utility at circuit level for timing violations for synchronous/asynchronous circuits. Useful for… Show more Worked as individual contributorDeveloped New toolsBlockarray : auto place and route utility for arraging blocks in row or column fashion for SOG/RAMLIB matrix.Preplace : preplacement utility for blocks, cannot occupy areas for SOG/RAMLIB matrix. Useful in floor-planning activity and detecting overlaps/out of matrix kind of checks.Sharp : setup/hold timing analysis utility at circuit level for timing violations for synchronous/asynchronous circuits. Useful for circuit integration at board level.Mebes : GDSII to MEBES mask format converter.Providespath expansion in GDSII to boundariessegmented MEBES mask format conversion of GDSIIinterface for HPGL plot for MEBES mask plottingGUI interface to support these activities.Added many enhancements to existing tools likemid2sim : add a new format to this netlister and delay file extractor utility for different simulator formats like HILO, EDIF etc. Data extracted through the internal database MIDAS. Show less

Worked as individual contributorDeveloped Windows based application and device driver for inhouse built pc-vcr controller card functioning through PC.Developed Windows based application for storing profile based information of a candidate like picture image, voice recording, signature.

Worked as individual contributorDeveloped parallel engine for PCB DRC using CDAC PC-add-on super4 (4 transputer) card for faster multiple layer processing