Co-Founder And Director
Current#Worked on SERDES 112GHz / 7nm layout & SERDES 56GHz /7nm#Worked on SERDES 28Ghz / 22FDX SOI#Worked on power management blocks in tsmc 16nm# Worked for APM for layout development on Analog IPs in 16nm.# Worked for Rambus RX blocks for SERDES 28Ghz / 14nm.#Worked on usb2.0 layout for a US based company in 28nm TX,RX and top level planning/integration.# Worked for Rambus Analog Layout development DDRPHY / 14nm# Worked for APM Layout development of SERDES 28Ghz / 16nm# Worked for Synopsys on Layout design of SERDES 16Ghz / 14nm #Worked for a startup company for Layout development of various blocks of LED driver IC in 250nm & 180nm technology different analog block ,IOs, ESD and IO ring development.#Worked for APM on Layout development SERDES - 28GHz / 28nm #Worked for Synopsys (Bangalore & Armenia team) high speed DDRPHY IO Layout development (14nm and 16nm Finfets) , # Provided training to Engineers of Infineon Technology on Analog,IOs, ESD and standard cells Layout development.# Worked for Xilinx Analog & IOs layout / 20nm tsmc.# Worked for Intel Mobile Communication (IOs Library layout development in 28nm).# Worked for APM Layout of PLL - 5GHz.# Worked for Rambus Layout development for memory interface for 3D chip.# Worked for Teranectics for DTV project layout development of PLL(9GHz), DATA & FSK DACs (4.5GHz)# Worked for MOSYS , Hyderabad for Layout development of synthesizer.LC & ring osc (5GHz), Voltage reg and integration.# Worked for Teranetics(aquired by PLX) layout development of High Speed SERDES (10GHz), RX, TX , REG, integration of analog portion of chip.# Worked for Infineon Technology for layout development of IO pads.# Worked for NXP for layout development of Class D amplifier 65nm tsmc
