Saumil Patel Email & Phone Number

San Jose, Ca, Us

San Francisco Bay Area

• For a customer-driven IP aimed at efficiently controlling voltage regulators for power conservationduring temperature changes, created the IP-level microarchitecture, designed power-efficient RTLfrom scratch using System Verilog, and successfully completed all Lint and CDC checks.• Designed and managed the comprehensive verification of the IP, I2C, and PMBUS protocols using assertions, regression testing, and integrating verification IPs on a UVM testbench.• Developed patterns and tests for post-silicon debugging on ATE and bench platforms, successfully demonstrating IP functionality to the external customer.

San Francisco Bay Area

• Leading the RTL TFM initiative within the Intel Networking group, aiming to incorporate the latest technologies in SoC front-end RTL design processes. The ultimate goals are to shorten the design cycle, reduce memory usage, and minimize post-silicon bugs.• Collaborating with multiple EDA vendors to identify and implement new technologies on SoCs, conducting weekly review sessions with each vendor’s application engineers.• Engaging with various product teams to understand their workflows and challenges, equipping them with the latest tools and processes for quicker turnaround times.

San Francisco Bay Area

• Led a team of four verification engineers to design and develop test-chip SoC verification, including all IPs and external customer IPs from the ground up. Successfully verified and delivered four test-chips on the latest Intel foundry nodes to customers.• Received recognition from C-suite executives for one of the test-chips, marking it as the first chip ever from any Intel team on that process node.• Designed and developed a multi-die verification environment, incorporating three dies on a package, multiple TAP networks, and I2C targets for voltage regulator control.• Created test content and verified DFT in RTL using the TAP network, and developed post-Si ATE tests for all IPs in the test-chip.

San Francisco Bay Area

RTL Design Feature Lead:• Led multiple features with a scale of approximately 3.2 million gates, impacting 18 units. Responsibilities included collaborating with architects to define the feature, preparing documentation, coordinating with unit owners for design and implementation, initial test writing, and overseeing end-to-end verification.• Part of a two-person team managing all Display post-silicon filings, which involved analyzing issues, eliminating test/environment problems, isolating issues to specific units or functionalities, identifying the root cause in RTL, collaborating with architects to find a viable software workaround.• Served as the single point of contact with the DFT team to implement a new post-silicon observability methodology across all Display Units, ensuring a transparent transition for Unit owners. This effort was recognized as the largest execution in scale and magnitude within the entire Graphics department.RTL Design:• Owned six Arbiter Unit designs (~2 million gate count each) across two live projects, three in the ECO phase, and two in post-silicon phase projects. • Designed two Arbiter Units that were 100% parameterized to accommodate changes in the number of clients and features per client for future projects.• Skilled in developing power-efficient RTL designs using RTL Clock Gating and Power Compiler Clock Gating.Verification:• Developed and owned the test environment for the cluster, and created a test suite to validate designs through waveforms and random regressions.• Proficient in System Verilog assertions and formal property verification, covering approximately 30% of validation using these methodologies.• Managed a cluster including Generators, BFMs, wrappers, and integrated checkers & assertions that facilitated the validation of multiple units.

M.S, Electrical & Electronics Engineering

B.E, Electronics & Communication Engineering