Academic background in microwave/RF, analog and digital IC CMOS design & layout.Analog design/verification, layout and EM design experience. Highly motivated, enthusiastic and communicative.Layout experience: - Analog Baseband Circuits: Bandgap/LDO, Tempsense, Level Shifters etc-High Speed and RF circuits: TX Driver/FFE , High Speed FF/Latches, High Speed ADC-Megacells and Chip Finishing: TX/RX, XTAL, Process Monitor, High Speed ADC Chip @100Gbps , Beamforming Chip, PLL-RF Layout Experience: CapBank/VCO, MIXQUAD, LNA, PA, Buffers, Mux, V2T-Design of Passives @20GHz: Lines, Lange Coupler, Lumped Hybrid, Quadrature hybrid coupler, Combiner 2to1-Custom ESD Layout -Advanced EMIR and Delta Voltage verification.-ESD/LUP solver for advanced nodes(16nm/7nm/3nm).-Baseband Digital Circuits.-EM Design/Layout and verification.-Modeling: PLL using Verilog – ATechnologies:-BiCMOS: iHP 130nm (SiGe) -Rad Hard Process: LF 180nm -CMOS (Planar): TSMC 65nm/45nm/28nm/22nm -CMOS(FDSOI): GF 22FDXTM, Samsung LNR28FDS-CMOS(Finfet): TSMC N16, N7/N3 - double pattern