Quality and Reliability Engineer: Dec 2018- Present• Work on defining spec requirements and ensure that all the stakeholders implement them.Work on DPM Calculation to predict yield and coverage analysis for all Products. • Actively work with all product teams to ensure they understand the specs and implement them accordingly.• Invest time in experimental and research work for improving the Test definitions and to catch issues before the product ships to customer.SOC Design Engineer : April 2015 -Dec 2018• Working on achieving 99% scan coverage target goals by ATPG DFT flows/Methodologies and focusing on lesser pattern count for both stuckat and transition faults. The analysis was done at all levels of designs in SCAN and functional path. • The target was to minimize ATPG content to maximize defect detection, scan insertion techniques on all IP, and DFT timing techniques. Debugged GLS (Gate level simulation) mismatches in simulations of RTL, Gate, and standard cell silicon stuck mismatches, vdd sensitivities, running ATPG pattern diagnosis, tracing logic in DFT tools. Debugging simulations in VCS with wave tools and ATPG tools for silicon debug of failing ATPG tests using Mentor Graphics Tessant (FastScan and TestKompress) tools. Currently working on Core CPU (LSSD design) and Uncore IPs (MUX D design) for 14nm technology and 10nm to report the Coverage Analysis using DFT Flow right from checking the Scan Insertion of the APR deliverables, DRC rules until the Pattern Generation which can finally be used on tester after GLS passes.