Office of the CTO - Research into differentiating technology solutions.

Technology Research : pathfinding integration for <5nm.

Technology Research - novel module integration for 7nm and beyond. Pathfinding device and integration for <7/5nm.

Technology Research : pathfinding integration for <10nm.

I worked predominantly on III-V MOSFET device engineering for post-silicon CMOS.We used two main device strategies:• A rapid turnaround device for qualifying materials, oxides and architectures and the effects of device processing. This work has resulted in surface channel quantum well structures with outstanding transport characteristics (IEEE EDL, http://dx.doi.org/10.1109/LED.2011.2107876).• A fully self-aligned device to explore feasibility of Si-like device fabrication and… Show more I worked predominantly on III-V MOSFET device engineering for post-silicon CMOS.We used two main device strategies:• A rapid turnaround device for qualifying materials, oxides and architectures and the effects of device processing. This work has resulted in surface channel quantum well structures with outstanding transport characteristics (IEEE EDL, http://dx.doi.org/10.1109/LED.2011.2107876).• A fully self-aligned device to explore feasibility of Si-like device fabrication and device characteristics. (http://dx.doi.org/10.1116/1.3501355)I also worked on nanoscale HEMTs for mm-wave applications. Show less

• Development of ultra-short gate length High Electron Mobility Transistor (HEMT) technology. These devices are of importance in millimeter-wave imaging and sensing applications in particular, with a need for low noise, high frequency performance. In addition, various HEMT-based technologies have been reported as potential candidates for future CMOS solutions, hence transport in nanoscale III-Vs is of interest.• Realised a robust sub-25 nm T-gate device fabrication process for… Show more • Development of ultra-short gate length High Electron Mobility Transistor (HEMT) technology. These devices are of importance in millimeter-wave imaging and sensing applications in particular, with a need for low noise, high frequency performance. In addition, various HEMT-based technologies have been reported as potential candidates for future CMOS solutions, hence transport in nanoscale III-Vs is of interest.• Realised a robust sub-25 nm T-gate device fabrication process for high-yield device fabrication (http://dx.doi.org/10.1016/j.mee.2008.01.058), and explored methods for 10 nm Lg device processing (http://dx.doi.org/10.1016/j.mee.2008.12.029). • My work involves cleanroom fabrication techniques, with an emphasis on high-resolution electron beam lithography and reactive ion etching.• This work has been funded by the Engineering and Physical Sciences Research Council. Show less

• Internship based on 6-month industrial Masters placement, jointly supervised at IBM and at University of Glasgow.• Development of a reactive environmental control system for open microfluidics ( http://www.dx.doi.org/10.1039/b515528m ). My work involved mixed-signal systems design and programming for environmental sensing and microcontroller control of Peltier modules to dynamically calculate and track the ambient conditions, preventing condensation and evaporation in an open… Show more • Internship based on 6-month industrial Masters placement, jointly supervised at IBM and at University of Glasgow.• Development of a reactive environmental control system for open microfluidics ( http://www.dx.doi.org/10.1039/b515528m ). My work involved mixed-signal systems design and programming for environmental sensing and microcontroller control of Peltier modules to dynamically calculate and track the ambient conditions, preventing condensation and evaporation in an open microfluidic system.• This work enabled the development of ultra-low flow rate open microfluidics for long-term microassays. Show less