Scott Matlock Email & Phone Number

Santa Clara, California, Us

Lead System Engineer leading a team of 50+ engineers to test and validate a unique low power APUDuties include:- Work with the engineering teams to create test plans to fully cover customer H/W and S/W use cases- Drive alignment between H/W validation, Firmware development, Operating System development, and Software QA and test- Review and align all Silicon coverage test plans- Work with Business and Production teams to align validation and production streams- Work with customer to address critical validation and H/W compliance issues- Work with System Program Management to complete all AMD validation work threads- Drive all critical program observations to root cause and help in developing workarounds and fixes

Kista, Stockholm, Se

Debug Lead for 5G Baseband and Radio ASICs

Santa Clara, California, Us

Managed a team of 15-20 validation and debug engineers working on Client PC productsRole included:Debugged critical System Level issues blocking production of Mobile platformsManaged a team of debuggers working on next generation mobile platforms. This included managing dozens of issues in parallelManaged a team of validation engineers creating and executing system validation plans for Mobile products

Santa Clara, California, Us

Director, Design Engineering at AMDLead System Engineer leading a team of 50+ engineers to test and validate a unique low power APUDuties include:- Work with the engineering teams to create test plans to fully cover customer H/W and S/W use cases- Drive alignment between H/W validation, Firmware development, Android OS development, and Software QA and test- Review and align all Silicon coverage test plans- Work with Business and Production teams to align validation and production streams- Work with customer to address critical validation and H/W compliance issues- Work with System Program Management to complete all AMD validation work threads- Drive all critical program observations to root cause and help in developing workarounds and fixes

Santa Clara, California, Us

Technical Lead for Tier 1 Graphics customer. Duties include:- Lead a team of Application Engineers in three geographic regions- Provide Design, Debug, and Platform Engineering support to the customer- Drive all gating H/W issues to resolution before product production

**SARC IP Design Debug**Debug complex SoC failures or performance issues for SARC provided IP- ARM 64-bit V8 (A57) compatible cores- LPDDR4 Memory Controller- Coherent FabricDevelop software utilities and scripts to validate and then enable all SoC DFD blocks. Includes C, C++, Python, and Lauterbach PRACTICE scripting. IP blocks included:- Coresight blocks- Custom Debug buses and on chip analyzers - Packet based debug tracingDevelop scripts to assist Soc power and Performance groups in debugging, performance analysis, and power measurements.Designed and built (schematic capture and layout) custom high speed dynamic current measurement board that allowed real time code correlation to the occurrence of a power spikeDeveloped c-code and Practice scripts to isolate performance bottlenecks in the buffer and switch fabric. Worked with the fabric designer to analyze and understand the data.

Santa Clara, California, Us

Served as a technical lead to validate and enable APU products for the Ultra Low Power (ULP) market segment. This includes:- Helped to define feature sets of the APU with a focus on platform cost and power reduction- Helped to architect a reference platform to showcase the unique features of the ULP APU- Helped to architect a validation platform to effectively test, debug, and characterize a ULP APU- Led a team of validation architects to ensure all critical APU features were fully validated- Worked with Customer Enablement teams to ensure platform feature sets were properly documented so customer design teams could optimize their platforms for performance and power.- Represented the Platform Engineering organization in technical syncs with OS vendors, third party H/W and S/W vendors

Santa Clara, California, Us

Technical lead (manager) of eight engineers in the system debug department. - Responsible for all external customer issues (Server, Desktop, and Notebook)- Provided detailed resolution reports back to the customer- Provided H/W fixes, BIOS, S/W and OS patches as necessary to the customer - Mentored the younger engineers on technical subjects as well as providing advice on career advancement

Houston, Texas, Us

**Server Storage Design Group**• Design of Redundant Array of Independent Disk (RAID) controllers. Position required the following activities:o Researched and designed applicable I/O subsystem to support the storage protocol required (Parallel SCSI, SAS)o Researched and designed applicable processing subsystem to support RAID levels (Embedded CPU cores)o Researched and designed appropriate memory subsystem to support data processing requirements (DDR, DDR II)o Schematic capture using ViewLogic softwareo Worked with layout engineer to ensure routing constraints had been met (Impedance, length, separation, etc)o Worked with Signal Integrity engineers in validating high speed nets (eye opening, jitter, ringing, overshoot, etc)

Houston, Texas, Us

**Industry Standard Servers (ISS) Hardware Engineering Problem Resolution (EPR) group**• Supported the Enterprise, Corporate, and Small/Medium Business Server Design Groups. Provided Hardware Engineering Analysis and debug of design related issues from the field, requiring detailed knowledge of Pentium Processors, Multi Processor Busses (P6), SMP techniques, MESI cache designs (L2 and L3), and ASIC designs. Also required detailed knowledge of Computer I/O busses (ISA, EISA, PCI, PCI-X, and PCI-e), Networking Technologies (Hubs, Switches, etc.), and Network Operating Systems (Microsoft, Netware, OS2, Linux). In addition, the position required detailed use of various types of test equipment, such as digital oscilloscopes, high-speed logic analyzers, current probes, network analyzers, and bus analyzers (PCI, SCSI, Ethernet).• Provided debugging support of latest server design projects. • Provided engineering analysis of third party vendor designs used on HP servers.• Resolved PCI compliance issues from the field on third party boards.• Designed specialized test equipment not available from Tektronix and Agilent. Wrote all the logic analyzer setup and display files.

Houston, Tx, Us

**Motorola IRIDIUM project in Chandler, Arizona**• Provided Engineering support in the Systems Integration and TestDepartment requiring detailed knowledge of the Iridium Space Vehicle (Satellite) and associated processes.• Provided configuration of Special Test Equipment (STE) requiring aworking knowledge of wireless digital communications.• Assisted in problem resolution using Spectrum Analyzers, Vector Analyzer, and Tektronix High Speed Logic Analyzer.**Shuttle Avionics Integration Laboratory (SAIL) at Johnson Space Center, Houston, TX: SAIL Engineering** • Designed both Digital and Analog equipment to replace obsolete simulation hardware, requiring detailed knowledge of the following:o Computer systems interfacing techniques, computer system I/O and processor busses, computer system interrupt architectures, serial busses and protocols, Analog to Digital (ADC), Digital to Analog (DAC) techniques, and system instrumentation design (RTDs, pressure transducers, thermocouples, etc.) o Designed Computer Systems for the various simulation laboratories, requiring extensive knowledge of computer systems hardware, software, and operating systems. The position also required detailed knowledge of various shared memory techniques, networking technologies, I/O busses, and computer systems interrupt hardware.

Houston, Tx, Us

Debugged and resolved all simulation hardware issues. Had detailed knowledge of Computer Systems and simulation H/W. This included Real Time computer main frames, Space Shuttle Simulation data acquisition H/W(DAC & ADC), VME based Single Board Computers, Space Shuttle digital data interfacing H/W, and Space Shuttle Simulation Instrumentation H/W (Thermal Couple, RTD, speed sensors, etc.).Also served as Lead Engineer and managed a group of Debug Engineers and Technicians.

Bachelor Of Science (Bs), Computer Engineering

General Studies, Pre Engineering