Martin Scott Email & Phone Number

San Francisco, CA, US

Menlo Park, California, United States

Menlo Park

Following the acquisition of Cryptography Research Inc. (CRI) in SF, and the Payments & Ticketing team in Europe, I took on multiple leadership roles. Key highlights include: - Grew revenue by ~3X post acquisition, creating market leadership for side-channel protected secure silicon IP and key provisioning during manufacturing- Broadly advocated a "chip to.

Managed the R&D investment portfolio to reduce costs and increase ROI across new initiatives in solid state lighting, computational imaging, context aware mobile media, storage acceleration, as well as directing the traditional memory and high-speed interface work. Ultimately refocussed core R&D on the changing memory interface needs at scale in data.

Led multiple technology diversification efforts to broaden the company's licensing portfolio including multimedia, solid state lighting, and computational imaging. Formed Rambus Labs to reinforce innovation while addressing the strategic need to manage risks in patent licensing

Integrated teams and design flows across all of engineering to improve productivity and quality while completing the interface designs on Sony PlayStation. Centralized design infrastructure to enable scaling and helped build the India Design Center into a critical delivery organization. Implemented test chip methodologies to accelerate learning on.

Led the integration of the I/O Solutions Division from Avago Technologoies into PMC's Storage Division which ultimately drove significant growth at PMCS. I then managed the Microprocessor Products Division, winning a large ASIC design, before being recruited into Rambus.

Drove significant growth in a high-speed storage networking chip and board business with top market share in FibreChannel. Developed 10G TOE and iSCSI products to address the growth of converged ethernet networks.

Led an ASIC and ASSP business focused on high-speed networking and servers. Leveraging HP legacy technology capability, I was instrumental in helping build Cisco into a major ASIC account at Agilent based on best-in-class SerDes performance and high-end chip design methodologies.

First managing the California Design Center and then combined with Ft Collins and Corvallis, I led the design and tape-out of ASICs consumed in HP products including servers, workstations, inkjet and laser printers, testers, and medical equipment.

Led the design, layout, tool installation, turn-on and ramp of a research fab built to accelerate the development and low-volume manufacturing of PA-RISC CPUs

Worked at Toshiba on 8-inch DRAM yield and lived in Japan on loan from HP

Performed solid state materials research in HP Labs across a wide range of developments including III-V bulk and epitaxial crystal growth, silicon micro-defect/ device behavior correlation for yield enhancement, and novel low thermal budget process equipment development. Built and managed a state-of-the-art characterization lab supporting R&D and line.

M.S., Ph.D., Materials Science & Engineering

Bs, Mechanical Engineering

Education record

Part of a one year HP Accelerated Development Program for High Potential Managers