Ser Seong Ng Email & Phone Number

Singapore

Singapore

Lead and manages current active semi custom products System Level Test program planning, evaluation, development and resource planning to ensure product success.Drive for High Volume Manufacturing KPIsImprove data analytic efficiency with innovative data visualization program such as PowerBI to streamline and standardize the team analysis workflow that got adopted and implemented company wide.Mentor and guide junior team members to fully understand the concepts and motivations behind every tasks and works assigned.

Singapore

System Level Test Engineer Debug and manage manufacturing and characterisation test programs for next-generation AMD semi custom microprocessors.Perform system level test (SLT )Test program integration, validation and release for high volume manufacturing (HVM) operation.To manage product yield, test time to meet target and drive initiatives for yield or test time improvement.

Penang, Malaysia

Led debug task forces across sites and provided debug next step and solution to resolve customer gating issues.Involved in various SoC interface system level functional debug for post product launch customer issues such as USB, Power Management, I2C, SVID, SDIO, PMIC with interaction with BIOS, Firmware and Driver in OS environment.Showcased debug technicalities in regional customer enabling workshop by correlated 68% of known silicon bug, discovered 2% of new bug and identified 3% of bug that requires fine tuning on customer systems. Receives multiple recognition of departmental exceptional & superior achievement award for excelling at customer satisfaction with on site customer support.Provided debug support for OEM & ODM customers to resolve the mass production build gating, shipment holding issues, compliance certification failure. Developed debug scripts for Intel next generation SoC power on activities

Penang, Malaysia

Delivered and executed test plan, methodologies, scripts and test execution for 2 generations of Intel chipsets high speed I/O (USB3.0) to meet both industrial compliance and internal product release qualification requirements.Owned content development and test plan for signal marginality validation on Intel test chip power on activity and successfully identified 2 DFx related bug.Successfully root caused and resolves new stepping gating silicon issues by collaborating with system validation team to intercept the design changes.Conducted the initiation for device qualification Tx compliance test for new test methodology on next generation intel chipset.Enabled new topology such as M.2 and Intel RealSense camera validation test methodology.

Conducted and carried out electrical validation test cases for Intel next generation chipsets I/O interfaces as contract workers. Troubleshooting on platform level setup with system hardware assembling, operating system installation, BIOS programming and test case implementations.Completed and arranged electrical test execution on Intel next generation chipsets according to time frame as planned and supported multiple out of scope debug request to achieve product release requirement.Converted as Intel permanent employees prior contract completion.