Shrihari G Email & Phone Number

Austin, Tx, Us

- Working on the architecture and micro-architecture of machine learning accelerators

Austin, Tx, Us

- Working on Workload-based Power-Energy Optimization on FDSOI systems- Currently, performing studies for deriving optimal design-time strategies driven by optimal workload based run-time strategies for digital subsystems consisting of RISC-V CPUs, ML Accelerators, IO Peripherals, CPU+Accelerators

Austin, Tx, Us

- Modeled a next-generation Low Power Machine Learning on the Edge Accelerator, and profiled across several TFLite-Micro Models, deriving insights about the architectural features and comparisons with earlier architectures, and external IPs- Architected mitigations for special cases and worked on the initial stages of the micro-architecture- Developed RTL for the compute engine in the IP, verified with a System Verilog Testbench, and performed a dry run of synthesis. - Optimized the micro-architecture to achieve 20% lower power and reduced area

Austin, Tx, Us

- Course: EE306 Introduction to Computing Systems- Held weekly problem solving sessions and re-enforced fundamentals- Developed grading scripts and graded programming labs

- Developed "1st CLaaS for PYNQ FPGAs" mentored by Steve Hover, Founder - Redwood EDA, and Theodore Omtzigt, Founder - Stillwater Super Computing- 1st CLaaS on PYNQ, brings the use model of 1st CLaaS, a framework for accelerating workloads with FPGAs on Cloud, by streaming data through web protocols to PYNQ FPGAs, but with the capabilities of RPAHX (Rapid Prototyping of Hardware Accelerators on Xilinx FPGAs), an automation framework to quickly prototype a hardware accelerator and integrate on a Zynq/Microblaze based design on Xilinx FPGAs. - The framework also has automated scripts to set up and securely expose your local FPGA to the internet, through Cloudflare Zero Trust on your own domain!

Coimbatore, Tamil Nadu, In

- Offered tie-ups to High schools in the state for Robotics and Embedded Workshops- Organized and deliver hands-on sessions- We have delivered talks to over 400 students and held workshops for over 120 students

Austin, Tx, Us

- Developed custom features to support legacy projects in Silicon Labs Design Environment- Integrated conditional compilation of firmware based on test cases and migrated Redpine Development Flow to Silicon Labs Design Environment- Developed golden reference models for AES-256 in CTR and XTS Modes.- Developed tests for testing security engine on QSPI Flash and PSRAM Controller by Integrating AES-256 XTS and CTR golden reference models - Automated regressions and integrated the custom features with regression runs on Jenkins- Researched AXI Protocol and Silicon Labs AXI (SLAXI) Protocol, and proposed improvements- Worked on Internal VCs for ARM Low Power Interface, Silicon Labs Peripheral Reflex System and SPI- Worked on GPIO Muxing and automated testbench generation for demux logic used in Verification Testbenches- Worked on Formal Verification environment bring up in upcoming projects

Chennai, Tamil Nadu, In

- Developed Co-processor Interconnects for RISC-V Processors based on the Core-V extension Interface- Integrated the interconnect in a RISC-V CPU, and tested with a dummy hardware accelerator- Updating SoC generation frameworks to support interconnect generation

Doctor Of Philosophy - Phd, Computer Engineering

Master Of Science - Ms, Electrical And Computer Engineering

Bachelor Of Engineering - Be, Electronics And Communication Engineering

12Th Grade, Physics, Chemistry, Mathematics, Computer Science, French