• 2023-Present: Tech lead for next gen AMD Instinct AI product offerings ("MI" family)

Foundry Technology and Operations -- Leading Edge FinFET product developmentDriving yield, reliability, and performance for key cutting-edge AMD products with our foundry partners. • 2019: Lead product engineer from foundry team for 7nm AMD Radeon RX 5000™ series ("Navi") of gaming GPUs built on RDNA 1st generation architecture• 2020-2023: Product lead, taskforce champion for high volume 6nm-4nm Sony Game Console products, driving the product maturity ramp from NPI to mass production. As the product owner, I am the focal point for all foundry-related issues, and serve as the key P.O.C. across internal functional groups, including regular reporting up to execs. I drove double digit yield gains, DPPM improvements, qualified various new process elements and lithography techniques to reduce cost, while maintaining power, performance, yield, quality and reliability metrics.

• 2016-2017: GF 14nm and early TSMC 7nm product and testchip development• 2018: Yield owner for 7nm AMD Radeon Instinct™ MI60 "Vega" professional/datacenter graphics card and AMD Radeon™ VII discrete gaming graphics card -- first ever GPUs in 7nm

20nm Bulk and 14nm FinFET Technology Development - SRAM Memory Solutions Team• Proactively identified and resolved issues impacted parametric and defect limited yield, Vmin distributions, and device performance & variation for all foundry platform and custom SRAM bitcells for diverse foundry customers.• Delivered SRAM device solutions consistently surpassing performance and variation targets through deep-dive split and DOE analysis of parametric and sort data. • Co-developed SLM arrayed test structures to monitor local Idsat and Vt variation with high statistical confidence, enabling Vt-mismatch reporting and predicting SRAM Vmin at a reticle-level granularity.• Proposed and defended process changes through the PCRB process to address and improve SRAM issues. Led detailed technical discussions with various technical teams, high-level executives, internal and external quality teams, and customer foundry interface teams.• Continuously improved process capability metrics to meet Quality goals by developing automated fab inline trends trackers, identifying issues early to minimize WIP impact. • Led a cross-functional team to reduce electrical test time by factor of 10% through advanced DOE-based test algorithm optimization, maintaining data fidelity (measured through statistical hypothesis testing) – Achieved Lean & Six Sigma Green Belt certification for this project.• Key GLOBALFOUNDRIES representative to Rochester Institute of Technology Microelectronic Engineering department - member of their Industrial Advisory Board to advise on curriculum development and enrollment & retention growth to drive future talent pool of microelectronic engineers.

• AMD 28 nm node development for semi-custom products manufactured at TSMC.• Developed a prediction algorithm with 95% confidence to predict final metal electrical testing results from initial metal electrical testing employing statistical hypothesis testing.• Optimized product device targeting for maximum yield and performance.