Owned development of a Java based standalone end-to-end PCI Express (PCIe) architectural checker which established IP met verification criteria by reading output from Bus Functional Models (BFMs) and comparing against a set of defined rules.• Developed comprehensive verification plan with involvement from key stakeholders to cover the PCIe IP architecture features along with the Intel On-Chip System Fabric (IOSF) primary/sideband interface and PCIe 2.0 to 4.0 specification requirements.• Conceived and implemented a rule coverage methodology using custom assertion code and MySQL tables to track rules covered by tests, generating immediate feedback to IP teams in order to tailor their constrained random testing to cover verification holes.• Provided quick turnaround times for debug of tool, test, and design issues (less than 2 hours for 90%+ of the bugs filed) to ensure SoC and IP teams met or beat schedules.• Incorporated automatic checking of configuration register values taking into account register attributes, last written values, and hardware updated signals. Saved each project team over 12 months of effort to code and debug equivalent checking in tests and test benches.• Developed unit tests with JUnit using test driven development techniques in combination with saved test runs to enable rapid rule creation and to ensure architecture rules met quality standards prior to releases.• Wrote and maintained 1100+ architecture rules to enable IP and SoC teams to find 700+ design, component specification, and tool bugs.

Technical lead for team of 5-10 globally situated engineers which verified the Intel C620 series chipset (code name Lewisburg) with primary focus on the PCI Express (PCIe), internal fabric, and Audio IPs. Secondary focus on Primary to Side Band (P2SB), Serial Peripheral Interface (SPI), Real Time Clock (RTC), and Low Pin Count (LPC) IPs.• Oversaw cross organization reviews of tests and sequences for ten IPs with architecture, design, and validation members to identify critical areas to apply focus, resulting in a 33% decrease in the number of existing tests required to be ported.• Held test and sequence reviews of IP code to determine if intent was up to team standards, revealed several key areas that required extra feature coverage due to multi-IP interactions.• Managed and trained five contractors on established test porting and debug methods, allowing them to be effective within a week of joining team.• Responded to unexpected schedule challenge by quickly ramping up on the Platform Management Controller (PMC) architectural checker in order to support quickly approaching power on and tape out deadlines, learned PMC flows and rules within 2 weeks, and provided support to team by debugging test failures and enhancements due to firmware bugs and updates.

Member of a 3 person team performing verification of the Intel Atom C2000 chipset family (code name Avoton) in a multi core configuration.• Ported and enhanced three random test environments originally for 4 cores to fully utilize 8 cores which satisfied project requirements.• Maintained 12 random test pools generating over 1000 seeds per day and debugged failures.• Expanded the Serial Voltage Identification (SVID) monitor using SystemVerilog to enable extended checking of the SVID protocol and RTL behavior at the full chip level.• Supported the emulation team on a high priority bug by creating a test that demonstrated the interrupt generation from an error injection, allowing them to debug a sighting that was gating production release qualification.

Technical lead for team of 5 engineers which verified PCI Express (PCIe) and Intel On-chip System Fabric (IOSF) functionality of the Intel 5400 (dual processor Sandy Bridge-based Xeon chipset, code name Seaburg)• PCIe and IOSF technical lead for IP validation teams, providing input to verification and test planning and review, set test development and execution schedules, trained new hires and contractors in verification best practices, managed and mentored junior engineers.• Wrote PCIe and IOSF test plans for full chip verification, implemented configuration routines, and developed scripts to upload test information from CVS repository to internal web based bug tracking tool.• Led chipset co-simulation effort by collaborating with cross-organizational processor teams to verify bus protocol implementation compatibility prior to tape out. Received an award for discovering 2 processor bugs dealing with specification compliance prior to tape out.• Provided support in recreating post-silicon sightings in the pre-silicon environment by characterizing what system validation team observed into BFM transactions.• Improved coverage database performance by 5x for updates, metrics queries, and test to event correlation by streamlining table structures and data entry methods

Technical lead of a team of 5-7 engineers which verified the processor bus, core router, and PCI Express clusters for the Intel 5000 (dual processor Core-based Xeon chipsets, code name Blackford)• Co-authored 100+ page project methodology plan that detailed the verification environments, checking strategies, and tests.• Pioneered the project use of cluster (a group of units) verification as a step above unit and a step below full chip verification, resulting in an increase in test reuse and checking confidence when verifying intra-unit connectivity.• Promoted project use of assertion based verification to aid in design intent documentation and as a launchpad to formal property verification, increasing overall design confidence by helping uncover bugs that would not have been found by normal simulations.• Improved model build time by parallelizing non-dependent flows which provided a decrease in turnaround time from >1 hour to 15 minutes.• Created and implemented an automated system of event coverage tracking used by several following projects. Managed replicated MySQL databases to collate coverage results, generated daily coverage metrics from data allowing team members to make informed decisions on where to direct testing focus to plug verification plan holes and for project manager for coverage status.• Developed Perl script to read in and verify full-chip configuration settings, saving pre and post-silicon teams hours of debug time by ensuring use of legal configurations.

Technical lead for team of 3-6 engineers which verified the ia32 single note configuration of the Intel E8870 (dual processor NetBurst-based Xeon chipset.)• Developed VHDL test bench wrappers used by both ia32 and ia64 variants of the 82870 chipset, resulting in a major time savings for initial model bring up.• Owned validation effort of a logic analyzer test chip used in post-silicon debug, developed test plans, ran and debug tests, and communicated findings to designers. Discovered several critical bugs that would have prevented chip from functioning in the lab.• Managed and trained six direct reports for ia32 multi-node validation. Taught the team verification methodologies, methods to minimize test holes, and best coding practices which allowed them to be productive in under a week.• Led three member design validation strike team to focus on critical areas of the chipset design. Maintained random regressions, monitored coverage, and interacted with designers to tailor tests to reach 100% event coverage goals.• Developed Perl script to convert logic analyzer traces to a format that allowed replaying of stimulus in pre-silicon simulations, decreasing bug recreation and characterization time from 48+ hours to 2 hours..• Owned processor/chipset co-simulation effort to verify bus protocol implementations prior to tape out. Interacted with processor groups by coordinating regular meetings to discuss findings and strategies, and created simulation environments used by both groups.• Sat in on the yearly validation roundtable for two years as a resident expert to promote the methods used in processor/chipset co-simulations and to discuss common problems found and their solutions.