Shawn Mclean Email and Phone Number

Designed and implemented firmware for a 10G/40G optical PHYAdded support for FEC, redundant fail-over, auto negotiation, module detection, and 40G PCSAssisted applications in debugging tier 1 customer deploymentsProvided API to applications and SDK

• Designed advanced wavelength diversity module for the datapath portion of a next generation mobile backhaul application.• Coded and verified an ethernet packet generator with associated RMON function.• Verified 3.125G GTP SERDES loopback on a Xilinx Spartan-6 FPGA.

• Enhanced SOC programmable state machine logic for last three product cycles.• Designed and implemented an LCD controller application state machine for Digital Picture Frame product.• Integrated USB2.0 controller and PHY for currently shipping product.• Designed and implemented I2S audio hardware for next generation SOC.• Supported tapeouts at 130nm, 90nm, and 65nm.

• Designed camera processing pipeline for a low cost mobile display controller.• Wrote bit accurate models for YCbCr 4:2:2 scaler and fixed point colorspace conversion blocks.• Specified, coded, and verified host interface, BT-656 camera sensor interface, scaler, and YCbCr to RGB colorspace conversion RTL.• Built chip top level and verified camera processing operation using bit accurate models.

• Project Lead for 17M gate ASIC switch for a 10 channel SMP chipset• Designed memory and processor interfaces and lead team to first tapeout• Managed external P&R, DFT, and bring-up• Designed OC192 SerDes fabric interface for a 320G-switch fabric chipset• Authored specification, wrote and verified RTL for 1.5M gate FPGA• Authored reference design and validation platform for 40G and 160G switch fabric• Wrote contract with partner to develop processor subsystem and… Show more • Project Lead for 17M gate ASIC switch for a 10 channel SMP chipset• Designed memory and processor interfaces and lead team to first tapeout• Managed external P&R, DFT, and bring-up• Designed OC192 SerDes fabric interface for a 320G-switch fabric chipset• Authored specification, wrote and verified RTL for 1.5M gate FPGA• Authored reference design and validation platform for 40G and 160G switch fabric• Wrote contract with partner to develop processor subsystem and mechanicals, managed chassis and board design, layout, assembly, and fab• Designed FPGA RTL and verification and managed lab bring-up• The company was sold on success of silicon Show less

• Co-Designed SAR ASIC for a layer 3 ATM/Ethernet network switch• Responsible for the design of the ingress multiport MAC interface, packet FIFO, and ATM segmentation engine• Co-wrote ASIC specification, wrote RTL, synthesized, and verified functional operation• Designed OC12 Utopia, egress, cell header translation, and processor interface for an ATM switch ASIC• Co-authored specification, wrote RTL, verified logic, and synthesized for standard cell ASIC• Managed functional… Show more • Co-Designed SAR ASIC for a layer 3 ATM/Ethernet network switch• Responsible for the design of the ingress multiport MAC interface, packet FIFO, and ATM segmentation engine• Co-wrote ASIC specification, wrote RTL, synthesized, and verified functional operation• Designed OC12 Utopia, egress, cell header translation, and processor interface for an ATM switch ASIC• Co-authored specification, wrote RTL, verified logic, and synthesized for standard cell ASIC• Managed functional block integration of a high performance 10/100 Ethernet switching ASIC Show less