Sherif Osama Email and Phone Number

Digital IC Design and Verification TrackThe training gives expertise in digital design flow for ASIC including Verilog modelling, synthesis,minimization, standard-cell libraries, timing optimization, timing models, timing analysis &constraints, Clock Tree Synthesis, placement and routing, Signoff and chip finishing, and designfor testing. Regarding the verification and testing of digital systems, the SystemVerilog conceptssuch as Data types, Function, threads, Interfaces, randomization, Code Coverage, FunctionalCoverage and Assertion Based Verification are covered. In addition to OOP and HierarchalTestbenchs. UVM verification projects including components such as transaction, generator,configuration, sequencer, driver, monitor, …. also, faults in digital systems, test generation andtestable systems, and pattern generation and comparator circuits of the built-in-self-test. Inaddition, the VLSI and full custom IC design flow topics learned include design of complex digitalcircuits, PLA, Arithmetic Blocks, Memory Design, system interconnect, Clock Generators andSystem Level Integration and it is emphasizing principles such as power optimization, timinganalysis, and signal and power integrity issues. These modules are delivered by worldwideindustry experts and university professors. Through hands-on experience in the labs withindustry-standard CAD tools, the trainee successfully completes assignments and projects foreach course.CAD tools include: Synopsys’s flow (Design Compiler, Formality, Library Manager, ICC2,PrimeTime, VCS, Verdi), Siemens’s flow (Tanner EDA: S-Edit, L-Edit, W-Edit, Calibre), Questa,Intel’s Quartus, and Cadence Virtuoso.Languages: SystemVerilog, Verilog