Gursimran Singh Email and Phone Number

 Expertise in integration of a PMC in SoC. Work on Micro Arch level to define feature implementation.  Responsible for quality and timely integration of multiple IPs and Firmware in SoC and delivery to our customer. Expert in ECO post synthesis to fix bugs. Also a point of contact for ECO for multiple IPs.  Validate and modify the env for emulation and fpga runs. Enhanced and automated flows to speed up the integration and validation process.

 Providing scalable solutions, so that tests and coverage can be used across multiple project. Verify USB-typeC functionality for PCH chipset and CPU Validate the communication protocols between Power Management Controller (PMC- RTL+FW) in Chipset and CPU and the functionality of new features for future products (Desktop, Servers, Laptop and Mobile). Functionally verify the features owned, to make sure to cover as much corner cases as possible, to improve the quality of an IP (Functional Coverage). Propagated debug methodologies to increase team efficiency during critical project phase. Automated regression triage and reporting tools to improve team effectiveness.

 Primary liaison with external and internal Electronic Design Automation (EDA) vendors in representing IPs (Intellectual Property) requests/issues and defining the tool requirements. Design automation support for multiple design organizations across 4 international geographies. Areas of expertise include Register Transfer Level (RTL) and Gate Level Simulation (GLS), coverage analysis, debug acceleration and validation methodology coach.  Developed a robust flow to support GLS (unit level and timing level), made the changes to enable first ever partition flow, which reduces the debug effort and elaboration of netlist by 4x.  As x-propagation methodology expert for a design flow, I have supported 40+ IPs and was credited for finding multiple bugs prior to product manufacturing. Experience in advance level usage of Verilog Compiler Simulator (VCS), with good understanding of tool itself. Provided and arranged training on different features of VCS tool (testbench debug, coverage analysis and low power debug). Responsible for the stability of the tool throughout the project execution.  Maintained and enhanced the flow to make the validation more effecting by bucketing the errors. Also standardize the flow across the IPs, to reduce the effort of maintaining multiple flows. Expert in coverage methodology, responsible for development and deployment of new coverage flow across the IPs. Did automation on top of the flow to make the tool and flow more scalable and easy to use by the validation engineers. Enhanced the Computer Aided Design (CAD) tools Quality Assurance (QA) system for migration to newer version of tools, to be more effective and robust. Developed selection criteria for IP inclusion and published the methodology documentation for deployment of this process throughout the organization.

Website Management and Proctoring.

Certified course of VerilogUART was implemented using Verilog, which was simulated and synthesized using Xilinx and Modelsim.

Worked in GIS department on Network Engineer Software. Placement of various cards (Equipments and Structure) which help in completion of CDMA