MSEE Graduate from San Jose State University with Digital System Design as specialization. -- Experience in high and low level module design, RTL Verilog coding and logic generation, logic synthesis and static timing analysis for system on chip, gate level simulation, DFT, D-algorithm, BIST, JTAG and low power design techniques.-- Hands on experience in HDL coding Verilog, System verilog, UVM(Verification).-- Experience in using Xilinx, Cadence, Synopsys, Altera tool, Matlab, DSP, FPGA DE0 Nano SOC Board for Professional projects in University.-- Knowledge in Computer Architecture - MIPS, NIOS II Processor.-- Programming Languages: C, Python, Linux, Unix, VI editor tools.-- Documented and presented Project procedure, Verification and Technical papers.-- Strong interpersonal and Communication skills, Quick learner, problem solving/analytical thinking skills and a good team player. I believe and practice " Nothing ever comes to one that is worth having, except as a result of hard work" - Booker T. Washington.