Santosh Raghavan Email & Phone Number

Santa Clara, Ca, Us

Mountain View, California, Us

Developing the world's fastest AI inference solution in the market!Responsible for:- Power Optimization & Power Modeling of Silicon & Systems for AI/ML Workloads (like LLMs)- ASIC Low-Power Design Optimization & Technology-specific Design Methodology- Power v/s Perf Architecture Trade-off for Silicon & Systems Design- Power Delivery Network design & Power Integrity analysis of ASIC package & board- Technology & IP PPA Evaluation & Readiness Assessment for Next-Gen Silicon & Systems

Santa Clara, California, Us

- Technology Benchmarking and Big data analysis, Signal processing, Process improvement, and Technology pathfinding within Non-volatile Memory Development performance-cost constraints- Scripting and automating design flows (using Python and C++) to accelerate process and product development- Hardware Design Enablement and PDK/SPICE model development, DTCO/Technology Benchmarking, Digital Circuit Design (spice level, gate level, RTL level, synthesis and verification), Analog Circuit Design.

Carlsbad, California, Us

Advanced RF semiconductor device design, characterization, modeling for advanced CMOS, BiCMOS, HBTs, III-V and GaN HEMT devices for analog/mixed-signal/power applications• Development and design enablement of advanced 5nm CMOS technology, comparison with previous technologies and providing improved PDK and design environment• Developed full spectrum of BSIM/BSIMCMG based compact SPICE models for 14nm/16nm technology PDK currently used for designing PAM4 DSP high-speed optical interconnect and 5G wireless access transceiver products• Characterized advanced node CMOS FinFET devices covering I-V, C-V, high frequency S-parameters, flicker/thermal noise, and linearity/Intermodulation-distortion (IP3) measurements • Developed SPICE models for precision high-R resistors, ESD diodes, BJTs and capacitors• Designed custom test-chip for 14nm FinFET device technology for thermal and flicker noise measurements, parasitic capacitance measurement of precision high-R resistors, capacitors and diodes• Contributed to several Silicon to Simulation issues, and worked to identify root-causes for Silicon non-performance related to process technology and/or troubleshooting simulation issues across different platforms• Provided elaborate technology support to analog circuit design engineers to sort simulation issues and collaborated in developing design sign-off flows/procedures

Santa Barbara, Ca, Us

PhD graduate student at UCSB, Materials Engineering.Advisor: Prof. Susanne StemmerDomain: Growth and Characterization of Oxide Semiconductor Thin Films For Advanced ElectronicsAuthored 17 journal publications (5 first author and 12 co-author)Presented at 5 conferences and gave 3 invited talks Detailed publication list: https://scholar.google.com/citations?user=CjhaHRgAAAAJ&hl=enResponsibilities and Achievements:• Lead and managed research projects, fabricated micro- and nano-scale oxide semiconductor devices in cleanrooms• Characterized materials quality using numerous materials analysis tools, designed materials for device applications• Maintained operation and troubleshooting of high-end mechanical and electronic equipment for group laboratoriesSelected Projects:1. “Molecular Beam Epitaxy of High Mobility Perovskite Oxides”• Developed a novel growth technique for high quality BaSnO3 semiconductor thin films. Demonstrated highest reported room temperature mobilities that are of interest for higher efficiency RF and power devices2. “Probing the Metal-Insulator Transition in BaTiO3 by Electrostatic Doping”• Established fundamental understanding of interplay between ferroelectricity and metallicity at reduced dimensions, with implications for all ferroelectric materials• Demonstrated a 3 unit cell lower limit for scaling in ferroelectric-based electronic devices 3. “Hybrid MBE growth of high quality defect-free RTiO3 and RTiO3/SrTiO3 heterostructures”• Developed the hybrid CVD-MBE technique to rare-earth (R) perovskite titanates • Enabled fundamental understanding of pseudo gaps, strong electron correlations, Mott-Hubbard insulators, symmetry related metal-insulator transitions, ferro- and anti-ferromagnetism at reduced dimensions, and highest charge gating oxide transistors.

Lausanne, Vaud, Ch

Masters graduate student at EPFL, Materials Engineering.Advisor: Prof. Nava SetterDomain: Ferroelectric Materials for Advanced ApplicationsAuthored 2 first author journal publicationsPresented at 1 conferences and gave 1 invited talkProjects: 1. “Retention Behavior in Graphene - Ferroelectric FETs for Memory Applications” • Investigated the effect of ferroelectricity on graphene and fabricated high-speed non-volatile FET-based memories with long-term retention properties2. “A DFT Study of SrTiO3 – Water Interfaces” • SrTiO3 – Water interface was modelled to find wet electron states facilitating electron transfer at the interface• These results explain the phenomenon which will help in fabricating efficient SrTiO3 photo-catalytic electrodes for water splitting. 3. “Fabrication and Evaluation of Organic Field-Effect Transistors (OFET)”• Fabricated OFETs based on two materials, Pentacene and P3HT (semiconducting polymer) at EPFL and CSEM (Swiss National Research Institute, Basel)• Achieved results helped in obtaining high-performance and low-cost OFETs, suitable for applications such as TFT (thin film displays), electronic readers and RFID chips

Navi Mumbai, Maharashtra, In

"Reliability Analysis of Steam Reformer Tubes in Hydrogen Plant"• Developed a new Remnant Lifetime Assessment method for RIL plant’s reformer tubes, improving assessment of creep degradation and allowing better scheduling of plant shut-downs and reduced equipment down-time

Doctor Of Philosophy (Phd), Materials Engineering

Course, Machine Learning, Deep Learning

Master Of Science, Materials Science

Bachelor Of Technology (B.Tech.), Materials Science