Power Management Architect for Intel Xeon products across current and next generation CPUs. Recognized as the bridge between IP, SoC and system level power management.• Lead Power Architect for Xeon CPUs • Leading power management software architecture initiative forum• Driving unified software interface for SOC features across multi-generations• Develop and maintain active and idle power management algorithms• Latency optimization of various core and SoC idle power states• System level power management interface and algorithm• Application aware optimization of the HW, FW and SW• Cross-functional collaboration with engineering teams, marketing and customers• Ongoing paranoia review and risk analysis and tracking of deliverables • Everyday Mission is simply – improving perf/watt/$ for Intel products• Lead Power Management firmware engineer for Xeon Phi for HPC market. Responsible for PM firmware architecture, design, modeling, verification, debug and validation for the Xeon Phi product line.

Led system BIOS team in various desktop and server BIOS projects, responsible for defining and developing system BIOS features, driving code/design reviews, root causing issues and implementing fixes, mentoring, planning, resource management, plans and executes the BIOS release milestones, providing current status along with risks, metrics, and responsible for the coordination and management of the BIOS team's efforts.

Lead BIOS and validation engineer teams for notebook and desktop products for DTK Computer Inc and AMI BIOS-Taiwan.