Management of ASIC and MEMS device design, MEMS process development, MEMS modeling, compensation algorithms, IC design, CAD, Engineering Compute and Packaging. ASIC design management included analog design, digital design, layout, AMS simulation, DFT and silicon validation. Also responsible for test engineering management for 1 year including remote site in Kuala Lumpur Malaysia. Managed RADAR R&D including design and SiGe process development for 1.5 years. Responsible for driving initiatives including innovation disclosures, mentoring and technical enrichment . Responsibility for remote design sites in Ridgeland MS, Toulouse France, Noida India, Munich Germany, Irvine CA, Milpitas CA, Detroit MI, Campinas Brazil, Moscow Russia and Sendai Japan. Have lead organizations from small teams to global organization of over 250 heads.

Site Director, IC Technical Lead, mixed-signal IC designer. As site director management of IC design, CAD, Engineering Compute, Program Management. IC design management included analog design, digital design, layout and silicon validation. Worked with other Cadence design sites on multi-site efforts including Livingston Scotland, Columbia Maryland, Cary North Carolina and San Diego California.

Site Director, IC Technical Lead, mixed-signal IC designer. As site director management of IC design, CAD, Engineering Compute, Program Management. IC design management included analog design, digital design, layout and silicon validation. Worked with major semiconductor companies (TI, Harris Semiconductor, AMI) as contract design house. Also performed library and circuit design for US Government agencies.