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Steven Shen Email & Phone Number

Design Engineer and Project lead at Xilinx
Location: San Jose, California, United States 6 work roles 1 school
1 work email found @xilinx.com LinkedIn matched
✓ Verified May 2026 4 data sources Profile completeness 100%

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Current company
Xilinx
Role
Design Engineer and Project lead
Location
San Jose, California, United States
Company size
1766 employees

Who is Steven Shen? Overview

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Quick answer

Steven Shen is listed as Design Engineer and Project lead at Xilinx, a company with 1766 employees, based in San Jose, California, United States. AeroLeads shows a work email signal at xilinx.com and a matched LinkedIn profile for Steven Shen.

Steven Shen previously worked as Design Engineer / Project lead at Xilinx and Sr. Member of Technical Staff/ Project Lead in Design at Altera. Steven Shen holds Ph.D., Electrical Engineering from Texas A&M University.

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Email format at Xilinx

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{first}.{last}@xilinx.com
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Profile bio

About Steven Shen

Many years of experience in design, architecture, and system application from well-known semiconductor companies.• Extensive design, architecture, system experience in ASIC/FPGA, and PHY Transceiver for SATA, SAS, PCI-Express, 1G/10G/40G/100G Ethernet, XAUI, Fibre Channel, SONET.• Extensive experience in FPGA emulation before silicon tape-out.• Extensive experience in chip bring-up and characterization in Lab.• Experience in SOC design for storage application.

Listed skills include Asic, Debugging, Verilog, Functional Verification, and 9 others.

Current workplace

Steven Shen's current company

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Xilinx
Xilinx
Design Engineer and Project lead
San Jose, CA, US
Website
xilinx.com
Employees
1766
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6 roles · 31 years

Steven Shen work experience

A career timeline built from the work history available for this profile.

Design Engineer And Project Lead

Xilinx

San Jose, CA, US

Design Engineer / Project Lead

Current
Xilinx

Virtex 7 Transceiver design/verification/Timing Closure/Characterization in 28nmVirtex 8 Transceiver design/verification/Timing Closure in 20nm

2010 - Present ~16 yrs 4 mos

Sr. Member Of Technical Staff/ Project Lead In Design

Altera

. Next generation Stratix-V family design and architecture for PCIE Gen-3 8.0Gbps PCS/PMA and upper layers. Supported Stratix-IV GX family successfully transciever roll out with PCS design, verification for TLP/DLL/PhyMac with BFM, memory with ECC verification with mram model, and pre-silicon gate-level simulation.. Supported successful roll out of.

2004 - 2009 ~5 yrs

Sr. Mts/ Lead Architect

Silicon Bridge Inc.

. SOC chip design with ARM946E for Storage Network. Quad-Channel Multi-Functional Transceiver architect/design, and characterization for Gen1/Gen2 SATA and SAS Host/Device 1.5G/3G with SSC, and PCI-Express Gen1 2.5G PHY with PCS layer. XGMII to XAUI 10GE (3.125Gbps x 4), Ring-Oscillator Based PHY architect/design, and characterization. XENPAK-like 10G.

2000 - 2004 ~4 yrs

Staff Engineer

Nec Electronics

. Octal-Channel Multi-Gigabit SERDES architect, Verilog Model design. Project Lead for Gigabit Ethernet Server NIC with GMAC testchip design (demo in the INTEROP, and passed UNH IOL lab tests). ASIC design for 8-port MAC and Customize 10/100/1000 Ethernet MAC. IEEE 802.3 standard meeting

1997 - 2000 ~3 yrs

Senior Engineer

Texas Instruments

. Ethernet and Token Ring Combo device debug, test suits development, and non-intrusive Sniffer design.. Packet Blaster design, and debug for ultra throughput improvement.. Embedded MAC microcode design, debug, switch architecture analysis, and FIFO improvement. IEEE 802.5 standard meeting

1995 - 1997 ~2 yrs
Team & coworkers

Colleagues at Xilinx

Other employees you can reach at xilinx.com. View company contacts for 1766 employees →

YK Young Kwon Young Kwon Colleague at Xilinx San Jose, California, United States, United States View → JM John Mitchell John Mitchell Colleague at Xilinx San Ramon, California, United States, United States View → CV Christopher Vu Christopher Vu Colleague at Xilinx Morgan Hill, California, United States, United States View → VL Vino Laureta Vino Laureta Colleague at Xilinx Metro Manila, National Capital Region, Philippines, Philippines View → ED Eddy De Waegeneer Eddy De Waegeneer Colleague at Xilinx Ghent Metropolitan Area, Belgium View → RS Raji Sundararajan Raji Sundararajan Colleague at Xilinx San Jose, California, United States, United States View → CN Ct Ng Ct Ng Colleague at Xilinx Singapore, Singapore View → TH Thomas Hynes Thomas Hynes Colleague at Xilinx Ireland, Ireland View → BS Brian Silverman Brian Silverman Colleague at Xilinx Cranford, New Jersey, United States, United States View → JC John Cross John Cross Colleague at Xilinx Canada, Canada View →
1 education record

Steven Shen education

FAQ

Frequently asked questions about Steven Shen

Quick answers generated from the profile data available on this page.

What company does Steven Shen work for?

Steven Shen works for Xilinx.

What is Steven Shen's role at Xilinx?

Steven Shen is listed as Design Engineer and Project lead at Xilinx.

What is Steven Shen's email address?

AeroLeads has found 1 work email signal at @xilinx.com for Steven Shen at Xilinx.

Where is Steven Shen based?

Steven Shen is based in San Jose, California, United States while working with Xilinx.

What companies has Steven Shen worked for?

Steven Shen has worked for Xilinx, Altera, Silicon Bridge Inc., Nec Electronics, and Texas Instruments.

Who are Steven Shen's colleagues at Xilinx?

Steven Shen's colleagues at Xilinx include Young Kwon, John Mitchell, Christopher Vu, Vino Laureta, and Eddy De Waegeneer.

How can I contact Steven Shen?

You can use AeroLeads to view verified contact signals for Steven Shen at Xilinx, including work email, phone, and LinkedIn data when available.

What schools did Steven Shen attend?

Steven Shen holds Ph.D., Electrical Engineering from Texas A&M University.

What skills is Steven Shen known for?

Steven Shen is listed with skills including Asic, Debugging, Verilog, Functional Verification, Fpga, Soc, Embedded Systems, and Serdes.

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