Steven Shen Email & Phone Number

San Jose, Ca, Us

Virtex 7 Transceiver design/verification/Timing Closure/Characterization in 28nmVirtex 8 Transceiver design/verification/Timing Closure in 20nm

. Next generation Stratix-V family design and architecture for PCIE Gen-3 8.0Gbps PCS/PMA and upper layers . Supported Stratix-IV GX family successfully transciever roll out with PCS design, verification for TLP/DLL/PhyMac with BFM, memory with ECC verification with mram model, and pre-silicon gate-level simulation. . Supported successful roll out of Stratix-II GX with full pre-silicon emulation and design Memory-Based, and MAC emulation platforms. Attended PCI-Express SIG Workshop, and got PCIE Gen2 certification . SATA OOB design and verification with squelch detect. Created characterization plan, co-managed cross-function char. activities. Setup emulation team in Penang

. SOC chip design with ARM946E for Storage Network . Quad-Channel Multi-Functional Transceiver architect/design, and characterization for Gen1/Gen2 SATA and SAS Host/Device 1.5G/3G with SSC, and PCI-Express Gen1 2.5G PHY with PCS layer. XGMII to XAUI 10GE (3.125Gbps x 4), Ring-Oscillator Based PHY architect/design, and characterization. XENPAK-like 10G channel LC-Tank-Based SERDES to XAUI chip architect, Eval board design and characterization. Managed customer IP licensing activities, and participated in the IEEE 802.3ae standard meetings

. Octal-Channel Multi-Gigabit SERDES architect, Verilog Model design. Project Lead for Gigabit Ethernet Server NIC with GMAC testchip design (demo in the INTEROP, and passed UNH IOL lab tests). ASIC design for 8-port MAC and Customize 10/100/1000 Ethernet MAC. IEEE 802.3 standard meeting

. Ethernet and Token Ring Combo device debug, test suits development, and non-intrusive Sniffer design.. Packet Blaster design, and debug for ultra throughput improvement.. Embedded MAC microcode design, debug, switch architecture analysis, and FIFO improvement. IEEE 802.5 standard meeting