Steven Garrison Email & Phone Number

San Jose, Ca, Us

Fremont Ca

FPGA design engineer working a contract at Cisco.

San Francisco Bay Area

Designed, implemented and lab debugged two large Xilinx Spartan-6 FPGAs for the CRS business unit.

I applied my FPGA expertise in the Optical Line Systems group.

Architected, designed, and implemented three generations of emulation platforms at Silicon Image. These boards were based on the following Xilinx FPGAs: Virtex2, Virtex4 and Virtex5.Wrote Verilog wrappers, simulation models, synthesis and build scripts, brought up designs on emulation boards to validate numerous products that Silicon Image has shipped in the 10s of millions of units.

Designed and implemented FPGAs for T1 and T3 line cards. One of the T1 cards FPGAs interfaced an Intel IXP1200 to a set of TI DSP chips. One of the FPGAs on the T3 card interfaced a PMC FreeDM chip to a GMII. The FreeDM interface is a variant of AnyPhy level 2. All designs were written in Verilog and placed and routed into Xilinx FPGAs ranging from the 9500 CPLDs to 1MegGate Virtex2 FPGAs. I assisted in setting high speed board layout design rules for outside PCB design house.

Designed and implemented a set of FPGAs on the access blades that are used for design and manufacturing verification. Three sets of FPGA designs were created to perform the following: a back-plane burst error rate test, an at-speed SRAM test and a board level connectivity test. The designs are written in VHDL, synthesized by Synplicity and placed and routed into a set of Lucent ORCA 2T and 3T FPGAs. Model Tech simulator was used to simulate and verify the designs.