Working as a VLSI Engineer with exposure in multiple domains and main focus on STA synthesis.Working in 5nm,3nm technologies.Hands on experience in FinFET technologies.Worked in Cadence Virtuoso for circuit designing and schematic simulation using HSpice.Hands on experience in various tools like ADE-L(Netlist Generation from Schematic),Viva-XL(Waveform Plotting),Worked with TSMC Mos transistors in 3nm technology.Thorough experience in CMOS transistor logic.Developed design and testbench codes… Show more Working as a VLSI Engineer with exposure in multiple domains and main focus on STA synthesis.Working in 5nm,3nm technologies.Hands on experience in FinFET technologies.Worked in Cadence Virtuoso for circuit designing and schematic simulation using HSpice.Hands on experience in various tools like ADE-L(Netlist Generation from Schematic),Viva-XL(Waveform Plotting),Worked with TSMC Mos transistors in 3nm technology.Thorough experience in CMOS transistor logic.Developed design and testbench codes using Verilog for various memory elements using Cadence Xcelium.Worked on basic layout of standard cells and combinational circuits like Latches and FlipFlops.Checked LVS and DRC using Calibre Mentoe Graphics.Generated CDL and GDS for layout techniques.Worked on Cadence Spectre for circuit simulation.Experience in using Cadence Liberate for generating delay templates of various elements used in SRAM.Experience in SRAM architecture 6T Bitcell.Working on STA synthesis using Genus and Innovus for timing analysis and keeping in focus PPAL(Power Performance Area Leakage).Worked on LVT and ULVT mac for performance.Carried out timing analysis for transmission gates,flipflop,latch,and,or,inverter,nand,nor gates,tristate inverters,clock generation for SRAM.Experience in TCL scripting language,Linux Shell Scripting.Skilled in MS Excel MS Office used in generating reports for the analysis I make. Show less

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