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Sumit Apte is listed as Senior Staff Physical Design Engineer at Qualcomm at Qualcomm, a with 37431 employees, based in San Diego, California, United States. AeroLeads shows a work email signal at qualcomm.com and a matched LinkedIn profile for Sumit Apte.
Sumit Apte previously worked as Senior Staff Physical Design Engineer at Qualcomm and Staff Physical Design Engineer at Qualcomm. Sumit Apte holds Bachelor Of Engineering (Be), Electrical, Electronics And Communications Engineering, Distinction - 77.10 % from University Of Mumbai.
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AeroLeads found 1 current-domain work email signal for Sumit Apte. Compare company email patterns before reaching out.
# 12 years experience in Netlist to GDS2 Physical Design flow. Successfully completed execution of multiple blocks. Worked on all sorts of designs ranging from 500 Mhz to 3Ghz+ and upto 6 million gate count with multiple tapeouts. Worked on 28nm, 16ff, 10nm, 7nm, 5nm & 4nm technology nodes.# Strong experience in RTL feedback required throughout design closure activity. Well versed with "ICC, ICC2 & Innovus" design tools.# Strong Experience in all aspects of IC design including Floorplanning, Power Planning, Clock Tree Insertion, Place and Route, Static Timing Analysis, Signal Integrity Analysis, ECO and Physical Verification.# Avid scripter with strong automation skills in tcl, csh, bash, icc_shell , pt_shell, innovus_shell.# Experienced in Block level data management, maintaining deliveries for top level.# Bachelor of Electronics 2011 batch, Mumbai University.# University Rank : 18th , Final year 78 % , Aggregate 74%
Listed skills include Physical Design, Static Timing Analysis, Floorplanning, Clock Tree Synthesis, and 30 others.
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San Diego, California, United States
Responsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
San Diego, California, United States
Responsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Bengaluru, Karnataka, India
Responsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Bengaluru Area, India
Responsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Bengaluru, Karnataka, India
Responsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Pune Area, India
*** Acquisition of LSI networking division by IntelResponsible for "Netlist to GDSII" Physical Design flow.- Working on industry leading technology, multi million gate count ASICs- Floorplanning, Placement, CTS, Routing (Synopsis ICC, Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Pune Area, India
Responsible for "Netlist to GDSII" Physical Design flow.- Worked on 28nm CMOS & 16 FinFET technology, multi million gate count ASICs- Floorplanning, Placement, CTS, Routing (Synopsis ICC)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Jon Luty
Colleague at QualcommSan Diego, California, United States
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Deepanshu Raj
Colleague at QualcommHyderabad, Telangana, India
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Anvita Tadepalli
Colleague at QualcommHyderabad, Telangana, India
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Yatharth Kochar
Colleague at QualcommSan Diego, California, United States
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Paramvir Prasad
Colleague at QualcommHyderabad, Telangana, India
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Tsering Lamo
Colleague at QualcommHyderabad, Telangana, India
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Darren Dickman
Colleague at QualcommSan Diego Metropolitan Area, United States
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Manish Kumar Dewangan
Colleague at QualcommHyderabad, Telangana, India
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Yurii Panchenko
Colleague at QualcommGreater Munich Metropolitan Area, Germany
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Sandeep J.
Colleague at QualcommIndia
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Quick answers generated from the profile data available on this page.
Sumit Apte works for Qualcomm.
Sumit Apte is listed as Senior Staff Physical Design Engineer at Qualcomm at Qualcomm.
AeroLeads has found 1 work email signal at @qualcomm.com for Sumit Apte at Qualcomm.
Sumit Apte is based in San Diego, California, United States while working with Qualcomm.
Sumit Apte has worked for Qualcomm, Intel Corporation, and Lsi Corporation.
Sumit Apte's colleagues at Qualcomm include Jon Luty, Deepanshu Raj, Anvita Tadepalli, Yatharth Kochar, and Paramvir Prasad.
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Sumit Apte holds Bachelor Of Engineering (Be), Electrical, Electronics And Communications Engineering, Distinction - 77.10 % from University Of Mumbai.
Sumit Apte is listed with skills including Physical Design, Static Timing Analysis, Floorplanning, Clock Tree Synthesis, Place And Route, Timing Closure, Drc, and Formal Verification.
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