Sumit Apte Email and Phone Number
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# 12 years experience in Netlist to GDS2 Physical Design flow. Successfully completed execution of multiple blocks. Worked on all sorts of designs ranging from 500 Mhz to 3Ghz+ and upto 6 million gate count with multiple tapeouts. Worked on 28nm, 16ff, 10nm, 7nm, 5nm & 4nm technology nodes.# Strong experience in RTL feedback required throughout design closure activity. Well versed with "ICC, ICC2 & Innovus" design tools.# Strong Experience in all aspects of IC design including Floorplanning, Power Planning, Clock Tree Insertion, Place and Route, Static Timing Analysis, Signal Integrity Analysis, ECO and Physical Verification.# Avid scripter with strong automation skills in tcl, csh, bash, icc_shell , pt_shell, innovus_shell.# Experienced in Block level data management, maintaining deliveries for top level.# Bachelor of Electronics 2011 batch, Mumbai University.# University Rank : 18th , Final year 78 % , Aggregate 74%
Qualcomm
View- Website:
- qualcomm.com
- Employees:
- 37431
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Senior Staff Physical Design EngineerQualcomm Nov 2024 - PresentSan Diego, California, United StatesResponsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Staff Physical Design EngineerQualcomm Apr 2022 - Nov 2024San Diego, California, United StatesResponsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Staff Physical Design EngineerQualcomm Dec 2021 - Mar 2022Bengaluru, Karnataka, IndiaResponsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Lead Physical Design EngineerQualcomm Dec 2018 - Nov 2021Bengaluru Area, IndiaResponsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Senior Physical Design EngineerQualcomm Jan 2017 - Nov 2018Bengaluru, Karnataka, IndiaResponsible for "Netlist to GDS II" Physical Design flow.- Working with team for development of futuristic products.- Working on industry leading technology and Designs across multiple domains- RTL Feedback ,Floorplanning, Placement, CTS, Routing (Cadence Innovus/Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
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Soc Design EngineerIntel Corporation Nov 2014 - Dec 2016Pune Area, India*** Acquisition of LSI networking division by IntelResponsible for "Netlist to GDSII" Physical Design flow.- Working on industry leading technology, multi million gate count ASICs- Floorplanning, Placement, CTS, Routing (Synopsis ICC, Synopsis ICC2)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre) -
Physical Design EngineerLsi Corporation Jun 2012 - Nov 2014Pune Area, IndiaResponsible for "Netlist to GDSII" Physical Design flow.- Worked on 28nm CMOS & 16 FinFET technology, multi million gate count ASICs- Floorplanning, Placement, CTS, Routing (Synopsis ICC)- Static timing analysis and closure (Synopsis PrimeTime)- DRC/LVS (Mentor Graphics Calibre)
Sumit Apte Skills
Sumit Apte Education Details
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Distinction - 77.10 %
Frequently Asked Questions about Sumit Apte
What company does Sumit Apte work for?
Sumit Apte works for Qualcomm
What is Sumit Apte's role at the current company?
Sumit Apte's current role is Senior Staff Physical Design Engineer at Qualcomm.
What is Sumit Apte's email address?
Sumit Apte's email address is su****@****ail.com
What schools did Sumit Apte attend?
Sumit Apte attended University Of Mumbai.
What are some of Sumit Apte's interests?
Sumit Apte has interest in Trekking, Video Games.
What skills is Sumit Apte known for?
Sumit Apte has skills like Physical Design, Static Timing Analysis, Floorplanning, Clock Tree Synthesis, Place And Route, Timing Closure, Drc, Formal Verification, Formality, Functional Verification, Physical Verification, Signal Integrity.
Who are Sumit Apte's colleagues?
Sumit Apte's colleagues are Manav S, Kanak Vijayvargiya, Pradeep Pant, A L, Alexandra Myszkowski, Joanne Ng, Gustavo Valencia.
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