Sumit Kumar Email & Phone Number

Senior Engineering Manager - SOC and IP Design Verification Manager• Good experience in ASIC/SoC and IP Verification in System Verilog and OVM, UVM Methodology.• Expertise in HDL & HVL languages such as Verilog, Vhdl , System Verilog and OVM , UVM Verification environments.• Leading the Design Verification for SOC’s project which includes SOC end to end design formal and functional verification. • Owning the entire design verification flow all test suits and over all metrics(code coverage ,functional coverage) on functional verifications • Cross-Functional Collaboration & Resource Management: Efficiently allocated team resources, balancing priorities and ensuring project deliverables• Mentoring Helping and guiding junior engineers /team members in technical and other flow improvements..