With a Master of Technology in VLSI and a passion for electronics engineering, I have developed strong skills and knowledge in FPGA, SoC, and IP verification, hardware security, and programming. I have also earned the Institute Gold Medalist honor for outstanding performance in my Master's program at Thapar University, where I gained a solid foundation in computer architecture, operating systems, PLC programming, and application-specific and integrated circuits. In my recent role as Research Fellow at IIT Delhi, I focused on developing solutions for enhancing the hardware system's security and improving its performance. In my role as a Design Verification Engineer at STMicroelectronics, I verified the debug block at sub-system level with C-based test cases, designed an asynchronous FIFO in Verilog, and implemented various AMBA protocols on System on Chip. I also developed UVM-based test cases and testbench environments for various IPs, and automated the verification process using scripts. As I embark on my journey in Australia, I am excited to apply my expertise and dedication to positions in the electronics industry, where I can collaborate with innovative teams, contribute to challenging projects, and embrace new opportunities for growth and development. I offer advanced Python, VHDL, Verilog, System Verilog, UVM, and programming languages knowledge, as well as a strong background in FPGA, embedded systems, and hardware security.