Teja P Email & Phone Number

Bangalore Urban, Karnataka, India

Project - Power Management ChipsMAR-2023Roles and responsibilities:1.Worked on Model Simulation and updated checkers for the blocks (GPIO, Failsafe,Anacore).2 Responsible for writing Verification plans for various blocks(LDO, TSD,BOOST)from specifications.3.Responsible for verify LDO, TSD,BOOST blocks with Schematic and Wreal models4.Responsible for testbench creation for behavioral and schematic Simulation.5.Responsible for writing checkers for behavioral and Schematic simulation

Bangalore Urban, Karnataka, India

Roles and responsibilities: • Extracted the netlist for all analog blocks in spice. • Created models of level-shifter, LDO, comparator, Clock generator • Created symbols and schematic for the subsystem level module • Perform Block level model vs schematic for simple blocks LPF/HPF in SMASH tool • Simulated subsystem integrating Digital block, Clock generator , BGR and LDO

Bengaluru, Karnataka, India

project-single port SRAM (JAN 2022-JUNE 2022)Roles and responsibilities: 1.schematic entry for a complete memory instance 2.Run Spice Functionality Simulation for READ, WRITE operation.3.Timing and power Sinulation of SRAM memory instance at different PVT conditions project-Dual port SRAM designRoles and responsibilities:1.Schematic entry for a complete memory instance 2.Run Spice Functionality Simulation for READ, WRITE operation.3.Timing and Power Simulation of SRAM memory instance at different PVT conditions

Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering

Design Verification, Engineering