Tejas Bhalla Email & Phone Number

Bengaluru, KA, IN

Bengaluru Area, India

• Full-fledged physical design implementation of timing and power critical mixed-signal hierarchical blocks with over ~20M gates, thousands of SRAMs, and multiple FUNC, DFT clocks in PHY ASICs at 16nm, 7nm & 5nm.
• Worked on chip-level physical design tasks including P&R and planning for IO ring, bumps, ESDs, and other ANA IPs
• Handled chip-level RH power-analysis including ESD resistance checks, IR and EM analysis
• Involved in various flow-enhancement activities… Show more
• Involved in various flow-enhancement activities such as PG improvements, timing-correlation, and glitch-power optimization Show less

Bengaluru Area, India

• Worked as a Design Intern in the Physical Layer Products (PLP) group, HSIP India Optical
• Familiarized with the complete RTL to GDSII work-flow in the group
• Responsibilities included physical design implementation, timing closure, physical and formal verification, power analysis of core digital blocks in PHY ASICs at 28nm & 16nm technology nodes

Koraput Area, India

Goa, India

Bachelor Of Engineering (B.E.), Electronics & Instrumentation

High School