Thomas Abbott
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Thomas Abbott Email & Phone Number

ASIC Design Engineer at Meta
Location: San Francisco, California, United States 9 work roles 2 schools
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✓ Verified Jun 2026 3 data sources Profile completeness 86%

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Current company
Role
ASIC Design Engineer
Location
San Francisco, California, United States
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Who is Thomas Abbott? Overview

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Quick answer

Thomas Abbott is listed as ASIC Design Engineer at Meta, a company with 5 employees, based in San Francisco, California, United States. AeroLeads shows a matched LinkedIn profile for Thomas Abbott.

Thomas Abbott previously worked as Graphics Hardware Engineer at Intel Corporation and Teaching Assistant at University Of California, Davis. Thomas Abbott holds Master Of Science - Ms, Electrical And Computer Engineering from University Of California, Davis.

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Meta

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Profile bio

About Thomas Abbott

I am a ASIC Design Engineer at Meta working on machine learning / AI datacenter accelerators. I graduated with a Master's of Science in Electrical and Computer Engineering from UC Davis in 2023. I wrote my thesis on JPEG Encoding, implementing it on my research group's many core processor, KiloCore. My thesis was subsequently published in IEEE. I have worked in various hardware engineering positions across Intel, Microsoft, and now Meta. I aim to continue my career as an RTL Designer.

Current workplace

Thomas Abbott's current company

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Meta
Meta
ASIC Design Engineer
aberdeen, aberdeenshire, united kingdom
Employees
5
AeroLeads page
9 roles

Thomas Abbott work experience

A career timeline built from the work history available for this profile.

Asic Design Engineer

Current

Sunnyvale, California, United States

Oct 2023 - Present

Graphics Hardware Engineer

Santa Clara, California, United States

- Did TFM work to create critical collateral for RTL freeze- Edited, improved, and executed test plans for three RTL features.- Debugged a critical issue gating RTL freeze

Jul 2023 - Oct 2023

Teaching Assistant

Davis, California, United States

  • Led laboratory sections of ENG 100 (Circuits II) and EEC 181A/B (Digital Design Senior Project)
  • Oversaw TPU design project: achieves 4.11x speedup in 4096x4096 matrix multiplication (100 MHz, Cyclone V DE-1 SOC)
  • Oversaw RISC-V design project: features pipelining, forwarding, and branch prediction (93 MHz, Cyclone V DE-1 SOC)
  • Oversaw bfloat-16 FPU design project: integrates with RISC-V ISA (90 MHz, ZedBoard Zynq-7000 SOC)
  • Organized weekly digital design challenge problems… Show more
  • Organized weekly digital design challenge problems, exploring Verilog fundamentals Show less
Sep 2022 - Jun 2023

Graduate Graphics Hardware Engineer Intern

Folsom, California, United States

- Worked full-time, assisting the Graphics Hardware Architecture team (hybrid)- Learned TAP (Test Access Port) methodology on the job via IEEE 1149.1 and 1167 specifications- Automated the TAP wiring hierarchy process by creating JSON and Python solutions- Considered timing and area constraints, and developed algorithms to maximize test clock frequency.

Jun 2022 - Sep 2022

Lsit Service Desk Analyst

Davis, California, United States

- Work part-time, 20 hours a week, while being a full-time student- Collaborate with UC Davis Faculty and Staff on technological problems both remotely and in-person- Closed over 1000 incidents to date.- Utilize and develop Mac and Windows OS skills- Troubleshoot workstations, laptops, printers, projectors, sound systems, scanners, and more- Lead remote.

Sep 2019 - Jul 2022

Silicon Design Engineer Intern

Sunnyvale, California, United States

- Worked full-time, remotely assisting Silicon Design frontend and backend teams.- Implemented Azure Dev Ops Pipeline-based regressions for the Design Team and CAD/Tools dev team- Collaborated 4 teams to leverage (and at times refactor) current tools to implement regressions- Learned Pipeline YAML schema, Bash, Ruby, TCL, KQL, PowerBI, and Make on the.

Jun 2021 - Sep 2021

Product Development Engineer

Folsom, California, United States

- Worked full-time for first six months, part-time for last two months (remote and in-person)- Participate in Agile Development with bi-weekly Sprint Meetings- Upkept a Kanban board and updated my daily progress on tasks- Automated 5 test flows via Python for security validation on future NVMe SSD products- Refactored 15+ test scripts to be more readable.

Jun 2020 - Feb 2021

Busser And Dispenser

I worked three summers in food service:- prepared sundaes- washed dishes- bussed tables- server's assistant

May 2017 - Sep 2019

Taag It Service Desk Anaylst

Davis, California, United States

I originally troubleshooted computers for The Arts Administrative Group at UC Davis, until Letters and Sciences IT absorbed TAAG IT.

Sep 2018 - May 2019
Team & coworkers

Colleagues at Meta

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2 education records

Thomas Abbott education

FAQ

Frequently asked questions about Thomas Abbott

Quick answers generated from the profile data available on this page.

What company does Thomas Abbott work for?

Thomas Abbott works for Meta.

What is Thomas Abbott's role at Meta?

Thomas Abbott is listed as ASIC Design Engineer at Meta.

Where is Thomas Abbott based?

Thomas Abbott is based in San Francisco, California, United States while working with Meta.

What companies has Thomas Abbott worked for?

Thomas Abbott has worked for Meta, Intel Corporation, University Of California, Davis, Microsoft, and Leatherbys Family Creamery.

Who are Thomas Abbott's colleagues at Meta?

Thomas Abbott's colleagues at Meta include Jose Ibarra, Artur Daniliuc, Keeseok Hong, Sebastien Speierer, and Madilyn Stevens.

How can I contact Thomas Abbott?

You can use AeroLeads to view verified contact signals for Thomas Abbott at Meta, including work email, phone, and LinkedIn data when available.

What schools did Thomas Abbott attend?

Thomas Abbott holds Master Of Science - Ms, Electrical And Computer Engineering from University Of California, Davis.

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