Thomas Bray Email & Phone Number

United States

Evaluating new IO technologies such as NVMe over TCP

Hopkington, Massachusetts

• System architecture design• Storage systems debug and design• Vendor relations • Certificate in PCIe, iSCSI protocols and Broadcom Stratix switches• Ethernet technologies • Ethernet Protocol Analysis• Knowledgeable in PCIe Gen 1, Gen 2 and Gen 3 protocol and design • Experienced with Ethernet Mac/Phy interfaces and offload Technologies • High-Speed system design and layout • Cadence, Concept and Allegro • Microsoft office sweet• Board bring up and Debug utilizing Tektronix Oscilloscopes Scopes, logic analyzers, W&G ANT 20 optical analyzer and Processor debuggers• Knowledge of PCB layout constraints and signal integrity under the Allegro PCB suite• Operating Systems – Windows and LINUX• Telecommunication Network standards (TDM/ATM/SONET)Responsibilities• Responsible for multiple Vendor relations and silicon selection driving next generation feature requirements in vendors silicon• Point of contact for all Ethernet vendors.• Responsible for all Ethernet issues and deliverables including hardware, firmware and drivers for all Business units• Creating and presenting internal silicon roadmap power points across all business units influencing next generation products• Responsible for architecting cutting-edge high-speed Ethernet solutions and management technologies for next generation platforms• Working across a multicultural and multi-product group environment to manage the interface between core engineering, vendors, and Business units• Responsible for FW deliverables and features between vendors, core engineering, and business units• Sustainability of all Ethernet and Fiber channel designs• Responsible for layer 1, layer 2, and layer 3 Ethernet protocol issues and analysis and debug working with the vendors• Debugging complex systems including firmware, driver and hardware issues

United States

Designed of a dual STM4/OC12, Quad STM1/OC3 TDM line card for ATCA based system including FPGA implementation design, schematic capture, and debug. Design, schematic capture, FPGA design, debug, and supporting documentation of an optical I/O modules (OC-3/STM-1, OC-12/STM-4, AU3/AU4 mappings) FPGA design of a GbE I/O moduleInvolved in the system architecture design of a next-generation ATCA platformAnalysis of optical systems for compliance with Telcordia standardsExperienced in high-speed clocking (STM-1, STM-4 and GbE)Experienced with PMC, Agere, Zarlink, and Vitesse communication ASICs (mappers, framers, HDLC controllers, TSI’s..etc) Experienced with TI DSPs (5441 and JANUS) implementing echo cancellation, CAS, and tone detection

Engineering Technology

Electronics