Tom Schaal Email and Phone Number

Design high performance memory subsystems for integration into Broadcom chip designs. Work involves RTL, verification, place and route, timng closure and post layout physical verification.

IC Physical Design Engineer.Multiple tape outs in 14nm SOI & 7nm EUV nodesz16 Telum processor L2 cache physical designz15 Themis processor L4 cache physical designz14 Midas processor L4 cache physical design7nm Samsung test chip physical design

IP development group. Projects worked on:1. DSP decimation filter2. ADC successive approximation controller3. IP integration into test chip top level design4. SerDes calibration controllers: Sample latch, Resistor, Clocks, AFE, Regulators5. SerDes adaptive equalization controllers: CTLE, DFE, AGC6. Physical implementation(layout and timing closure) of small digital blocks and test chips implemented in 28nm and 40nm nodes. During this time I wrote RTL, wrote and ran simulations for functional verification, synthesized RTL into gate netlists with SCAN test insertion, wrote timing constraints and ran STA, created and tested IP test wrappers, used Matlab for analysis and development, ran power simulations, performed block and chip level physical implementation including floor planning, place and route, timing closure, power analysis, DRC cleanup, extraction, noise analysis, etc. Chips released in 28m & 14nm nodes

ASIC physical design team lead engineer for telecommunication chips. My role was setup a design environment to implement the chips as needed by the design teams. As such, I selected tools, specified compute environment, selected foundry, libraries and IP.

Developing Next Generation IC design tool flow for 32nm, 22nm and 14nm technology nodes. The NextGen flow is an End To End(E2E) flow encompassing all tools required to take a design from RTL to OASIS. NextGen enables IC designs to use larger physical partitions, supports iterative hierarchy, reduces turn around time, reduces project personnel and compute resource requirements while maintaining sign off accuracy. All IC design groups across IBM are transitioning to the NextGen flow which will be the global IC design platform. Switching from transistor level to Gate Level Sign Off(GLSO) is key to enabling larger partitions. My responsibilities are developing the GLSO tools portion of the flow including extraction, timing analysis, noise analysis, power analysis(IR), electro migration(EM) and creating abstract views required for use at higher levels. Multiple 32nm and 22nm tape-outs achieved using new flow. Specific tasks performed: Scripting new & modified tools, features and sign off requirements into the flow using ksh, tcl, perl & skill code. Capture and run project designs of various hierarchies through the E2E flow testing changes. Modifying designs to cleanup problems so E2E flow can be run successfully. Modify regression scripts to support new tools and enhanced features.

Lead ASIC design teams implementing internal and external customer designs in 130nm, 90nm, 65nm and 40nm nodes. Design teams were composed of engineers located at various US and international locations. My expertise in ASIC development spans working with customers developing specifications through all design phases to a functioning part. Specific tasks performed: Worked with ASIC sales teams and customers defining projects by recommending IP, technology and packaging to minimize cost and meet performance goals required for end use product. Planned project resource requirements, people, skills, compute resources, tools and durations required for projects. Acquired IP from internal and external suppliers and managed release to customers. Assisted customers modifying their designs as needed to work with the IP supplied, modifications required for production test, supplied design kits and assisted with synthesis, simulation, timing analysis and scripting. Received RTL or netlists from customers and performed required steps to get netlist ready for layout including synthesis, test insertion, package checks, timing analysis constraints development. Chip floor planning, hierarchy partitioning, power planning, clock planning & insertion, time budgeting & layout constraint qualification. Chip and hierarchical block layout, formal verification, timing, noise, power, DRC/LVS, all design closure tasks. Scripted chip and block design flows for new netlists and ECOs, setup fixing scripts, DMSA hold scripts and all design closure tools. Created final checklists for IP, libraries, tools and flows, tests required for signoff. Worked with customers doing post layout verification and post silicon bring up and characterization. Developed Toshiba IP: wrote verilog RTL, performed design verification, library model development, layout, timing analysis, DRC/LVS for test chips and custom high speed digital blocks used in SATA/SAS/PCIE serdes upto 8.5Gbps.

Design services company specializing in FPGA and ASIC implementation. Worked with a variety of domestic and international companies. Provided architecture, design, verification, RTL coding, functional verification, synthesis, STA & FPGA prototyping services. Products included retail and oem electronic systems, subsystems and components.

Designed SONET OC-192 framer and switch ASICs. Performed RTL coding, functional verification and formal verification services.

Design services company specializing in FPGA and ASIC implementation. Worked with a variety of domestic and international companies. Provided architecture, design, verification, RTL coding, functional verification, synthesis, STA & FPGA prototyping services. Products included retail and oem electronic systems, subsystems and components.

ASIC design engineer responsible for design and verification of interface chips used in industry standard PCs and subsystems. Primary interfaces designed to were SCSI, ATA, PCI, parallel port. Established and provided ASIC design services at the Roy, Utah R&D campus.