Tyler Cao, Mba Email & Phone Number

United States

• Responsibilities:
• Program Manager for a 30+ global and cross-functional hardware design team that delivers high quality HW solutions required to validate the next generation of Intel x86 client CPU products. Owner of all aspects of.
• Reduced end user negative feedback by 80% with 70% fewer issue sightings by engaging with multi-discipline design teams and customers to improve overall efficiency, quality, and user satisfaction.
• Improved hardware design quality by 50% by fostering a learning organization and creating new organizational process assets that involved personally championing the creation of a board design checklist and board build.
• Utilized technical, analytical, and collaboration skills to lead task forces and coordination meetings to monitor deliverables and quickly resolve design challenges to enable silicon power-on & faster TTM.
• Delivered on-time, on-budget, and in-quality HW that included debug & characterization boards, DDR interposers, PCIe AOBs, and mechanical & thermal solutions for margining and system validation.

• Responsibilities:
• Manager of a team of 8 hardware design engineers delivering validation and manufacturing boards for the next generation of Intel x86 products, multi-discipline team consisted of layout engineers, design engineers.
• Achieved $250K+ per year cost savings by effectively driving the change from a forecast-based model to an on-demand model that optimized the CAD tools licensing for the 150+ employee organization.
• Reduced cycle time by 50% and cost by 75% on the PCB design library by leading process improvements and coordinating an internal library team of 3 employees and 2 outsourcing vendors for the creation of schematic and.
• Reduced board design time by 4+ weeks per project by leading a technical forum that developed and evaluated new CAD tools to increase capacity through automation and reuse.
• Defined the vision, mission, and strategies for the team to align on a shared purpose to efficiently provide high quality custom boards to the validation and manufacturing organizations, including component debug.

• Responsibilities:
• SI leader for a team of 6 engineers that delivered high-quality validation platform boards for x86 Xeon CPUs. Owner of all aspects of the SI design including schedule, simulation plan, stackup, routing guidelines.
• Reduced SI simulation effort by 6+ weeks per program by developing scripts & tools for analyzing serial and parallel interfaces, championed these tools to be adopted across Intel as best practices by promoting and.
• Enabled over-clocking CPU by 20% by performing and analyzing extensive DOE-based SI simulations to optimize critical high-speed interface topologies for component placement and board trace lengths.
• Provided high quality boards for testing and characterizing the latest Intel CPUs, ensured all bugs found in validation were real silicon issues and not board issues to enable faster product qualification & TTM.
• Contributed to the knowledge growth of the SI community within Intel by mentoring junior engineers and authoring 2 technical papers, “High-speed design optimization for QPI on Silicon Debug Platform”, and “Evaluation.

Master Of Business Administration In Finance (Mba), Business Administration And Management, 4.0 Gpa

Activities and Societies: Phi Kappa Phi, Beta Gamma Sigma• Completed MBA in Finance with focus on corporate finance, new venture finance.

Bachelor Of Science - Bs, Electrical Engineering