Umar Lyles Email & Phone Number

Austin, Tx, Us

Austin, Tx, Us

Austin, Texas Metropolitan Area

Responsible for leading team chartered with architectural exploration, modeling, model verification, AMS, and design verification. Collaborates with directors, senior managers and staff to define and implement best practices. Builds and trains teams (from 1-12 employees). Primary go-to lead for all tier 1 project execution. Maintains customer relationships and prepares reports for VP level staff. Architected tools to facilitate model development and verification and AMS execution and reporting, oversees their development and implementation. Audits development methodologies, writes proposals and implements process improvements. Developed modeling capabilities enabling true SPICE emulation in system Verilog environment (EEnet based) and developed fast prototyping model libraries. Architect of automated coverage driven model verification tool. Back fill roles when needed as design verification manager responsible for internal/external customer reporting, driving functional and code coverage & regression closure as well as chip design and integration lead.

Austin, Texas Area

Manage a global team of Design Verification Engineers (UVM)Own Verification aschedule Own risk identification and mitigation planningReport critical project metrics including regression status, coverage, and bug closure Provide debug support for SV

Austin, Texas Area

Own AMS schedule Own risk identification and mitigation planningReport AMS status and bug closure Manage and lead AMS-UVM setup, planning, and executionProvide SV-RNM and AMS modeling supportProvide AMS debug supportDevelopment and deployment of primitive EEnet models and systems including (boost/buck, hall-sensor, H-bridge inductive speaker, etc...)

Austin, Texas Metropolitan Area

Developed Verilog-AMS (vams) models for power integrated ICs. Setup AMS environment and executed AMS simulations. Expert reviewer for analog design blocks - provided feedback for architectural and design improvements. Wrote and presented proposals on migration plans to tops down model driven development methodology.

Austin, Texas Area

Driving organization wide adoption of contemporary AMS methodologies best practices. Trained jr engineers in analog design, system Verilog RNM and AMS modeling, and mixed signal methodologies. Managed remote contract team for delivery of AMS verification execution. Developed sv-RNM models performed model verification. Design of high precision 200MHz DCO for delta-sigma Phase lock loop (PLL). Design of gain and offset calibrated DAC for brown out detection Design of various analog circuits including I2C front end, POR, bias generators, etc…

Melbourne, Florida, United States

Contributed to development of system level solutions, coordinated design team efforts, owned design schedule, tracking risks, drove top-level layout, and provided progress updates to senior management for projects requiring mixed signal design teams of 2-9 engineers. Design of continuous and discrete time sigma-delta 10-16 bit ADC. Design of cold start state machine & boost charger for 300nA energy harvesting battery monitoring and charging IC. Design of various common analog blocks including LDO, buffer, charge pump, oscillators, band gaps, comparators, level shifters, analog MUX, etc…Optimized top level mixed mode verification with AMS. Scripting for batch mode regression runs using python/ocean/tcl and waveform viewing with simvision. • Project Management – Create and drive project schedule ensuring benchmarks and milestones are on track. Monitor risks and make analyses to minimize them. Effectively communicate progress updates on projects to senior management (requiring design teams of 2-9 engineers).• Circuit Design – Design circuits including LDO, buffer, charge pump, oscillator, band gap, comparator, level shifter, switch, MUX, continuous and discrete time Σ∆ 10-16 bit ADC, state machines, cold start boost charger, etc... for energy harvesting battery monitoring and charging applications.• Verification – Optimization of top level mixed mode verification with AMS. Scripting for batch mode regression runs using python/ocean/tcl and waveform viewing with simvision.• Applications – Provide customer support detailing IC architecture, behavior and custom integration methods.• Test – Perform bench checkout and debug of IC’s with standard laboratory equipment (DC sources, function generators, logic analyzers, probe stations, etc.)

Master Of Science (Ms), Electrical Engineering

Magna Cum Laude Thesis: Tracking Delta Sigma Injection Locked Direct Digital Frequency Synthesizer

Bachelor Of Science (Bs), Electrical And Electronics Engineering

Activities and Societies: National Science Foundation WAESO graduate fellowship recipientMagna Cum Laude